[llvm] r288188 - AMDGPU: Rename flat operands to match mubuf
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 11:30:44 PST 2016
Author: arsenm
Date: Tue Nov 29 13:30:44 2016
New Revision: 288188
URL: http://llvm.org/viewvc/llvm-project?rev=288188&view=rev
Log:
AMDGPU: Rename flat operands to match mubuf
Use vaddr/vdst for the same purposes.
This also fixes a beg in SIInsertWaits for the
operand check. The stored value operand is currently called
data0 in the single offset case, not data.
Modified:
llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td?rev=288188&r1=288187&r2=288188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td Tue Nov 29 13:30:44 2016
@@ -57,8 +57,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo
let AsmMatchConverter = ps.AsmMatchConverter;
// encoding fields
- bits<8> addr;
- bits<8> data;
+ bits<8> vaddr;
+ bits<8> vdata;
bits<8> vdst;
bits<1> slc;
bits<1> glc;
@@ -69,8 +69,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo
let Inst{17} = slc;
let Inst{24-18} = op;
let Inst{31-26} = 0x37; // Encoding.
- let Inst{39-32} = addr;
- let Inst{47-40} = !if(ps.has_data, data, ?);
+ let Inst{39-32} = vaddr;
+ let Inst{47-40} = !if(ps.has_data, vdata, ?);
// 54-48 is reserved.
let Inst{55} = tfe;
let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
@@ -79,8 +79,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo
class FLAT_Load_Pseudo <string opName, RegisterClass regClass> : FLAT_Pseudo<
opName,
(outs regClass:$vdst),
- (ins VReg_64:$addr, GLC:$glc, slc:$slc, tfe:$tfe),
- " $vdst, $addr$glc$slc$tfe"> {
+ (ins VReg_64:$vaddr, GLC:$glc, slc:$slc, tfe:$tfe),
+ " $vdst, $vaddr$glc$slc$tfe"> {
let has_data = 0;
let mayLoad = 1;
}
@@ -88,8 +88,8 @@ class FLAT_Load_Pseudo <string opName, R
class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass> : FLAT_Pseudo<
opName,
(outs),
- (ins VReg_64:$addr, vdataClass:$data, GLC:$glc, slc:$slc, tfe:$tfe),
- " $addr, $data$glc$slc$tfe"> {
+ (ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc, tfe:$tfe),
+ " $vaddr, $vdata$glc$slc$tfe"> {
let mayLoad = 0;
let mayStore = 1;
let has_vdst = 0;
@@ -105,8 +105,8 @@ multiclass FLAT_Atomic_Pseudo<
def "" : FLAT_Pseudo <opName,
(outs),
- (ins VReg_64:$addr, data_rc:$data, slc:$slc, tfe:$tfe),
- " $addr, $data$slc$tfe",
+ (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
+ " $vaddr, $vdata$slc$tfe",
[]>,
AtomicNoRet <NAME, 0> {
let mayLoad = 1;
@@ -119,10 +119,10 @@ multiclass FLAT_Atomic_Pseudo<
def _RTN : FLAT_Pseudo <opName,
(outs vdst_rc:$vdst),
- (ins VReg_64:$addr, data_rc:$data, slc:$slc, tfe:$tfe),
- " $vdst, $addr, $data glc$slc$tfe",
+ (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
+ " $vdst, $vaddr, $vdata glc$slc$tfe",
[(set vt:$vdst,
- (atomic (FLATAtomic i64:$addr, i1:$slc, i1:$tfe), data_vt:$data))]>,
+ (atomic (FLATAtomic i64:$vaddr, i1:$slc, i1:$tfe), data_vt:$vdata))]>,
AtomicNoRet <NAME, 1> {
let mayLoad = 1;
let mayStore = 1;
Modified: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp?rev=288188&r1=288187&r2=288188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp Tue Nov 29 13:30:44 2016
@@ -427,7 +427,7 @@ int GCNHazardRecognizer::createsVALUHaza
}
if (TII->isFLAT(MI)) {
- int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::data);
+ int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
return DataIdx;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp?rev=288188&r1=288187&r2=288188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp Tue Nov 29 13:30:44 2016
@@ -252,12 +252,6 @@ bool SIInsertWaits::isOpRelevant(Machine
// operand comes before the value operand and it may have
// multiple data operands.
- if (TII->isDS(MI) || TII->isFLAT(MI)) {
- MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::data);
- if (Data && Op.isIdenticalTo(*Data))
- return true;
- }
-
if (TII->isDS(MI)) {
MachineOperand *Data0 = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
if (Data0 && Op.isIdenticalTo(*Data0))
@@ -267,6 +261,12 @@ bool SIInsertWaits::isOpRelevant(Machine
return Data1 && Op.isIdenticalTo(*Data1);
}
+ if (TII->isFLAT(MI)) {
+ MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::vdata);
+ if (Data && Op.isIdenticalTo(*Data))
+ return true;
+ }
+
// NOTE: This assumes that the value operand is before the
// address operand, and that there is only one value operand.
for (MachineInstr::mop_iterator I = MI.operands_begin(),
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=288188&r1=288187&r2=288188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Tue Nov 29 13:30:44 2016
@@ -299,7 +299,7 @@ bool SIInstrInfo::getMemOpBaseRegImmOfs(
}
if (isFLAT(LdSt)) {
- const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::addr);
+ const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
BaseReg = AddrReg->getReg();
Offset = 0;
return true;
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