[PATCH] D27028: Add intrinsics for constrained floating point operations

[Andy Kaylor via Phabricator via llvm-commits]

andrew.w.kaylor updated this revision to Diff 79447.
andrew.w.kaylor added a comment.

I re-wrote the ISel code to introduce a pseudo-instruction for the strict variants of FP operations, which is mutated directly to a normal FP node just before instruction selection.  I removed the SDNodeFlag extensions I had added in my original patch because they aren't needed in this implementation.  Some variant of that code will likely need to be re-introduced at some point, particularly to handle FTZ rounding modes.

I did not introduce the code to add a target-specific implicit use of the FP-environment register.  I do intend to add this in a later patch, but this code works well enough without it that I believe it can be deferred.

At some point it will be necessary to teach the LegalizeDAG code how to handle the strict instructions in order to legalize strict FP nodes with vector operands.  I intend to do that in a later patch also.


Repository:
  rL LLVM

https://reviews.llvm.org/D27028

Files:
  docs/LangRef.rst
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAGISel.h
  include/llvm/IR/IntrinsicInst.h
  include/llvm/IR/Intrinsics.td
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  lib/IR/IntrinsicInst.cpp
  lib/IR/Verifier.cpp
  test/CodeGen/X86/fp-intrinsics.ll
  test/Feature/fp-intrinsics.ll
  test/Verifier/fp-intrinsics.ll

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