[PATCH] D26939: [AMDGPU] Fix multiple vreg definitions in si-lower-control-flow

[Stanislav Mekhanoshin via llvm-commits]

rampitec added a comment.

In https://reviews.llvm.org/D26939#602033, @arsenm wrote:

> Do you have a testcase where this was an issue? I though I got all of these when I moved the pass to SSA. Why isn't the verifier catching this?


Technically pass works post SSA, so it is not required to maintain SSA. It does not create errors (at least I'm not aware of errors caused by this), but results in MRI->getUniqueVRegDef() returning a null pointer. I'm working on combining two S_AND_B64 instructions in the snippet below and similar, and it if returns nullptr my code simply cannot do anything.

  %vreg20<def> = S_AND_B64 %EXEC, %vreg18, %SCC<imp-def,dead>; SReg_64:%vreg20,%vreg18
  %vreg46<def> = COPY %vreg19<kill>; VGPR_32:%vreg46,%vreg19
  %vreg3<def> = COPY %EXEC, %EXEC<imp-def>; SReg_64:%vreg3
  %vreg47<def> = S_AND_B64 %vreg3, %vreg20, %SCC<imp-def,dead>; SReg_64:%vreg47,%vreg3,%vreg20
  %vreg3<def> = S_XOR_B64 %vreg47, %vreg3, %SCC<imp-def,dead>; SReg_64:%vreg3,%vreg47


Repository:
  rL LLVM

https://reviews.llvm.org/D26939