[PATCH] D26939: [AMDGPU] Fix multiple vreg definitions in si-lower-control-flow

[Stanislav Mekhanoshin via llvm-commits]

rampitec created this revision.
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SI Lower control flow pass creates multiple definitions of virtual registers.

SI_IF:

  %vreg3<def> = COPY %EXEC, %EXEC<imp-def>; SReg_64:%vreg3
  %vreg47<def> = S_AND_B64 %vreg3, %vreg20, %SCC<imp-def,dead>; SReg_64:%vreg47,%vreg3,%vreg20
  %vreg3<def> = S_XOR_B64 %vreg47, %vreg3, %SCC<imp-def,dead>; SReg_64:%vreg3,%vreg47

SI_ELSE:

  %vreg2<def> = COPY %vreg0<kill>; SReg_64:%vreg2,%vreg0
  %vreg2<def> = S_OR_SAVEEXEC_B64 %vreg2, %EXEC<imp-def>, %SCC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg2
  %vreg1<def> = COPY %vreg20<kill>; VGPR_32:%vreg1,%vreg20
  %EXEC<def> = S_AND_B64 %EXEC, %vreg19<kill>, %SCC<imp-def,dead>; SReg_64:%vreg19
  %vreg21<def> = COPY %vreg1<kill>; VGPR_32:%vreg21,%vreg1
  %vreg2<def> = S_AND_B64 %EXEC, %vreg2, %SCC<imp-def>; SReg_64:%vreg2
  %EXEC<def> = S_XOR_B64_term %EXEC, %vreg2; SReg_64:%vreg2

This is the patch to fix SSA.


Repository:
  rL LLVM

https://reviews.llvm.org/D26939

Files:
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  test/CodeGen/AMDGPU/branch-condition-and.ll
  test/CodeGen/AMDGPU/valu-i1.ll

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