[llvm] r287541 - [SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Nov 21 08:36:19 2016
New Revision: 287541

URL: http://llvm.org/viewvc/llvm-project?rev=287541&view=rev
Log:
[SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/packss.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=287541&r1=287540&r2=287541&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Nov 21 08:36:19 2016
@@ -2874,6 +2874,13 @@ unsigned SelectionDAG::ComputeNumSignBit
       return ComputeNumSignBits(Op.getOperand(0), Depth+1);
     break;
   }
+  case ISD::CONCAT_VECTORS:
+    // Determine the minimum number of sign bits across all input vectors.
+    // Early out if the result is already 1.
+    Tmp = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
+    for (unsigned i = 1, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i)
+      Tmp = std::min(Tmp, ComputeNumSignBits(Op.getOperand(i), Depth + 1));
+    return Tmp;
   }
 
   // If we are looking at the loaded value of the SDNode.

Modified: llvm/trunk/test/CodeGen/X86/packss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/packss.ll?rev=287541&r1=287540&r2=287541&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/packss.ll (original)
+++ llvm/trunk/test/CodeGen/X86/packss.ll Mon Nov 21 08:36:19 2016
@@ -88,44 +88,22 @@ define <8 x i16> @trunc_ashr_v4i32_icmp_
 ; X32-SSE:       # BB#0:
 ; X32-SSE-NEXT:    psrad $31, %xmm0
 ; X32-SSE-NEXT:    pcmpgtd {{\.LCPI.*}}, %xmm1
-; X32-SSE-NEXT:    pslld $16, %xmm1
-; X32-SSE-NEXT:    psrad $16, %xmm1
-; X32-SSE-NEXT:    pslld $16, %xmm0
-; X32-SSE-NEXT:    psrad $16, %xmm0
-; X32-SSE-NEXT:    packssdw %xmm1, %xmm0
+; X32-SSE-NEXT:    packsswb %xmm1, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
 ; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
 ; X64-SSE:       # BB#0:
 ; X64-SSE-NEXT:    psrad $31, %xmm0
 ; X64-SSE-NEXT:    pcmpgtd {{.*}}(%rip), %xmm1
-; X64-SSE-NEXT:    pslld $16, %xmm1
-; X64-SSE-NEXT:    psrad $16, %xmm1
-; X64-SSE-NEXT:    pslld $16, %xmm0
-; X64-SSE-NEXT:    psrad $16, %xmm0
-; X64-SSE-NEXT:    packssdw %xmm1, %xmm0
+; X64-SSE-NEXT:    packsswb %xmm1, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
-; X64-AVX1-LABEL: trunc_ashr_v4i32_icmp_v4i32:
-; X64-AVX1:       # BB#0:
-; X64-AVX1-NEXT:    vpsrad $31, %xmm0, %xmm0
-; X64-AVX1-NEXT:    vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; X64-AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
-; X64-AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
-; X64-AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X64-AVX1-NEXT:    retq
-;
-; X64-AVX2-LABEL: trunc_ashr_v4i32_icmp_v4i32:
-; X64-AVX2:       # BB#0:
-; X64-AVX2-NEXT:    vpsrad $31, %xmm0, %xmm0
-; X64-AVX2-NEXT:    vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
-; X64-AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; X64-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
-; X64-AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; X64-AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
-; X64-AVX2-NEXT:    vzeroupper
-; X64-AVX2-NEXT:    retq
+; X64-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
+; X64-AVX:       # BB#0:
+; X64-AVX-NEXT:    vpsrad $31, %xmm0, %xmm0
+; X64-AVX-NEXT:    vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
+; X64-AVX-NEXT:    vpacksswb %xmm1, %xmm0, %xmm0
+; X64-AVX-NEXT:    retq
   %1 = ashr <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
   %2 = icmp sgt <4 x i32> %b, <i32 1, i32 16, i32 255, i32 65535>
   %3 = sext <4 x i1> %2 to <4 x i32>