[PATCH] D26793: [mips] Add support for unaligned load/store macros.

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with some nits addressed, and another set of test cases.

I'm seeing differences between GAS' output and LLVM's output when the immediate has to be loaded with loadImmediate. The difference (extra moves) is mostly cosmetic and I am not too concerned with them.



================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3325
   if (hasMips32r6() || hasMips64r6()) {
-    return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+      return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
   }
----------------
Nit, indentation.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3339-3340
 
-  // NOTE: We always need AT for ULHU, as it is always used as the source
-  // register for one of the LBu's.
   unsigned ATReg = getATReg(IDLoc);
----------------
Restore this comment.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3375
+  if (hasMips32r6() || hasMips64r6()) {
+      return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+  }
----------------
Nit, indentation.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3426
+  if (hasMips32r6() || hasMips64r6()) {
+      return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+  }
----------------
Nit: indentation.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3473
+  if (DoMove)
+    TOut.emitRRI(Mips::ORi, TmpReg, DstReg, 0, IDLoc, STI);
 
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This should be using the register variant of 'or'. This is more for consistency with the GNU and LLVM toolchain for moving the contents of one register. Also, add test cases to cover this case: ulw $8, <cst>($8).


================
Comment at: test/MC/Mips/mips-expansions.s:692
+  # CHECK-BE: ori       $1, $zero, 32768        # encoding: [0x34,0x01,0x80,0x00]
+  # CHECK-BE: move      $1, $1                  # encoding: [0x00,0x20,0x08,0x21]
+  # CHECK-BE: sb        $8, 1($1)               # encoding: [0xa0,0x28,0x00,0x01]
----------------
These moves aren't appearing from GAS' output. They're add's coming from loadImmediate.


Repository:
  rL LLVM

https://reviews.llvm.org/D26793