[llvm] r287049 - [x86] auto-generate better checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 15 15:01:11 PST 2016
Author: spatel
Date: Tue Nov 15 17:01:11 2016
New Revision: 287049
URL: http://llvm.org/viewvc/llvm-project?rev=287049&view=rev
Log:
[x86] auto-generate better checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/fast-isel-select-sse.ll
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-select-sse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-select-sse.ll?rev=287049&r1=287048&r2=287049&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-select-sse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-select-sse.ll Tue Nov 15 17:01:11 2016
@@ -1,341 +1,494 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX
; Test all cmp predicates that can be used with SSE.
define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_oeq_f32
-; CHECK: cmpeqss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_oeq_f32
-; AVX: vcmpeqss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_oeq_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpeqss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_oeq_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_oeq_f64
-; CHECK: cmpeqsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_oeq_f64
-; AVX: vcmpeqsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_oeq_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpeqsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_oeq_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ogt_f32
-; CHECK: cmpltss %xmm0, %xmm1
-; CHECK-NEXT: andps %xmm1, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm1
-; CHECK-NEXT: orps %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ogt_f32
-; AVX: vcmpltss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ogt_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpltss %xmm0, %xmm1
+; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm1
+; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ogt_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpltss %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ogt float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ogt_f64
-; CHECK: cmpltsd %xmm0, %xmm1
-; CHECK-NEXT: andpd %xmm1, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm1
-; CHECK-NEXT: orpd %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ogt_f64
-; AVX: vcmpltsd %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ogt_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpltsd %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm1
+; SSE-NEXT: orpd %xmm2, %xmm1
+; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ogt_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpltsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ogt double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_oge_f32
-; CHECK: cmpless %xmm0, %xmm1
-; CHECK-NEXT: andps %xmm1, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm1
-; CHECK-NEXT: orps %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_oge_f32
-; AVX: vcmpless %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_oge_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpless %xmm0, %xmm1
+; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm1
+; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_oge_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpless %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp oge float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_oge_f64
-; CHECK: cmplesd %xmm0, %xmm1
-; CHECK-NEXT: andpd %xmm1, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm1
-; CHECK-NEXT: orpd %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_oge_f64
-; AVX: vcmplesd %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_oge_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmplesd %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm1
+; SSE-NEXT: orpd %xmm2, %xmm1
+; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_oge_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmplesd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp oge double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_olt_f32
-; CHECK: cmpltss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_olt_f32
-; AVX: vcmpltss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_olt_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpltss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_olt_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpltss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp olt float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_olt_f64
-; CHECK: cmpltsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_olt_f64
-; AVX: vcmpltsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_olt_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpltsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_olt_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpltsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp olt double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ole_f32
-; CHECK: cmpless %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ole_f32
-; AVX: vcmpless %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ole_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpless %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ole_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpless %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ole float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ole_f64
-; CHECK: cmplesd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ole_f64
-; AVX: vcmplesd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ole_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmplesd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ole_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmplesd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ole double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ord_f32
-; CHECK: cmpordss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ord_f32
-; AVX: vcmpordss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ord_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpordss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ord_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpordss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ord float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ord_f64
-; CHECK: cmpordsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ord_f64
-; AVX: vcmpordsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ord_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpordsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ord_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpordsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ord double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_uno_f32
-; CHECK: cmpunordss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_uno_f32
-; AVX: vcmpunordss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_uno_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpunordss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_uno_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpunordss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp uno float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_uno_f64
-; CHECK: cmpunordsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_uno_f64
-; AVX: vcmpunordsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_uno_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpunordsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_uno_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpunordsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp uno double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ugt_f32
-; CHECK: cmpnless %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ugt_f32
-; AVX: vcmpnless %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ugt_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnless %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ugt_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnless %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ugt_f64
-; CHECK: cmpnlesd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_ugt_f64
-; AVX: vcmpnlesd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ugt_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnlesd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ugt_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnlesd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_uge_f32
-; CHECK: cmpnltss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_uge_f32
-; AVX: vcmpnltss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_uge_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnltss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_uge_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnltss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp uge float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_uge_f64
-; CHECK: cmpnltsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_uge_f64
-; AVX: vcmpnltsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_uge_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnltsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_uge_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnltsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp uge double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ult_f32
-; CHECK: cmpnless %xmm0, %xmm1
-; CHECK-NEXT: andps %xmm1, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm1
-; CHECK-NEXT: orps %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ult_f32
-; AVX: vcmpnless %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ult_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnless %xmm0, %xmm1
+; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm1
+; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ult_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnless %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ult float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ult_f64
-; CHECK: cmpnlesd %xmm0, %xmm1
-; CHECK-NEXT: andpd %xmm1, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm1
-; CHECK-NEXT: orpd %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ult_f64
-; AVX: vcmpnlesd %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ult_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnlesd %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm1
+; SSE-NEXT: orpd %xmm2, %xmm1
+; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ult_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnlesd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ult double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_ule_f32
-; CHECK: cmpnltss %xmm0, %xmm1
-; CHECK-NEXT: andps %xmm1, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm1
-; CHECK-NEXT: orps %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ule_f32
-; AVX: vcmpnltss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ule_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnltss %xmm0, %xmm1
+; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm1
+; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ule_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnltss %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ule float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_ule_f64
-; CHECK: cmpnltsd %xmm0, %xmm1
-; CHECK-NEXT: andpd %xmm1, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm1
-; CHECK-NEXT: orpd %xmm2, %xmm1
-; AVX-LABEL: select_fcmp_ule_f64
-; AVX: vcmpnltsd %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_ule_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpnltsd %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm1
+; SSE-NEXT: orpd %xmm2, %xmm1
+; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_ule_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpnltsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp ule double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
}
define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) {
-; CHECK-LABEL: select_fcmp_une_f32
-; CHECK: cmpneqss %xmm1, %xmm0
-; CHECK-NEXT: andps %xmm0, %xmm2
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: orps %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_une_f32
-; AVX: vcmpneqss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_une_f32:
+; SSE: # BB#0:
+; SSE-NEXT: cmpneqss %xmm1, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: andnps %xmm3, %xmm0
+; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_une_f32:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpneqss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp une float %a, %b
%2 = select i1 %1, float %c, float %d
ret float %2
}
define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: select_fcmp_une_f64
-; CHECK: cmpneqsd %xmm1, %xmm0
-; CHECK-NEXT: andpd %xmm0, %xmm2
-; CHECK-NEXT: andnpd %xmm3, %xmm0
-; CHECK-NEXT: orpd %xmm2, %xmm0
-; AVX-LABEL: select_fcmp_une_f64
-; AVX: vcmpneqsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; SSE-LABEL: select_fcmp_une_f64:
+; SSE: # BB#0:
+; SSE-NEXT: cmpneqsd %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: andnpd %xmm3, %xmm0
+; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: select_fcmp_une_f64:
+; AVX: # BB#0:
+; AVX-NEXT: vcmpneqsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
+; AVX-NEXT: retq
+;
%1 = fcmp une double %a, %b
%2 = select i1 %1, double %c, double %d
ret double %2
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