[llvm] r286913 - AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Nov 14 18:05:42 2016
New Revision: 286913

URL: http://llvm.org/viewvc/llvm-project?rev=286913&view=rev
Log:
AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*

This doesn't solve any problems I know about, but this should have
more conservative assumptions about the operands'

Modified:
    llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=286913&r1=286912&r2=286913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Mon Nov 14 18:05:42 2016
@@ -167,11 +167,13 @@ def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64
 
 def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
   let SchedRW = [WriteFloatFMA, WriteSALU];
+  let hasExtraSrcRegAllocReq = 1;
 }
 
 // Double precision division pre-scale.
 def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
   let SchedRW = [WriteDouble, WriteSALU];
+  let hasExtraSrcRegAllocReq = 1;
 }
 
 def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>;