[PATCH] D26577: [AVR] Add the pseudo instruction expansion pass

[Dylan McKay via llvm-commits]

dylanmckay created this revision.
dylanmckay added reviewers: kparzysz, arsenm.
dylanmckay added a subscriber: llvm-commits.
Herald added subscribers: modocache, mgorny, wdng.

A lot of the pseudo instructions are required because LLVM assumes that
all integers of the same size as the pointer size are legal. This means
that it will not currently expand 16-bit instructions to their 8-bit
variants because it thinks 16-bit types are legal for the operations.

This also adds all of the CodeGen tests that required the pass to run.


https://reviews.llvm.org/D26577

Files:
  lib/Target/AVR/AVRExpandPseudoInsts.cpp
  lib/Target/AVR/AVRTargetMachine.cpp
  lib/Target/AVR/CMakeLists.txt
  test/CodeGen/AVR/add.ll
  test/CodeGen/AVR/alloca.ll
  test/CodeGen/AVR/and.ll
  test/CodeGen/AVR/atomics/fence.ll
  test/CodeGen/AVR/atomics/load16.ll
  test/CodeGen/AVR/atomics/load8.ll
  test/CodeGen/AVR/atomics/store.ll
  test/CodeGen/AVR/atomics/store16.ll
  test/CodeGen/AVR/brind.ll
  test/CodeGen/AVR/call.ll
  test/CodeGen/AVR/cmp.ll
  test/CodeGen/AVR/com.ll
  test/CodeGen/AVR/directmem.ll
  test/CodeGen/AVR/dynalloca.ll
  test/CodeGen/AVR/eor.ll
  test/CodeGen/AVR/error-srcreg-destreg-same.ll
  test/CodeGen/AVR/expand-integer-failure.ll
  test/CodeGen/AVR/frame.ll
  test/CodeGen/AVR/high-pressure-on-ptrregs.ll
  test/CodeGen/AVR/inline-asm.ll
  test/CodeGen/AVR/interrupts.ll
  test/CodeGen/AVR/io.ll
  test/CodeGen/AVR/lit.local.cfg
  test/CodeGen/AVR/load.ll
  test/CodeGen/AVR/or.ll
  test/CodeGen/AVR/progmem.ll
  test/CodeGen/AVR/return.ll
  test/CodeGen/AVR/sext.ll
  test/CodeGen/AVR/store.ll
  test/CodeGen/AVR/sub.ll
  test/CodeGen/AVR/varargs.ll
  test/CodeGen/AVR/xor.ll
  test/CodeGen/AVR/zext.ll

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