[llvm] r286654 - ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCI
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 11 14:37:31 PST 2016
Author: matze
Date: Fri Nov 11 16:37:31 2016
New Revision: 286654
URL: http://llvm.org/viewvc/llvm-project?rev=286654&view=rev
Log:
ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCI
Push VRegUses/collectVRegUses() down the class hierarchy towards its
only user ScheduleDAGMILive.
NFCI: The initialization of the map happens at a later point but that
should not matter.
This is in preparation to allow DAG mutators to merge nodes, which
relies on this map getting computed later.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=286654&r1=286653&r2=286654&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Fri Nov 11 16:37:31 2016
@@ -379,6 +379,9 @@ protected:
MachineBasicBlock::iterator LiveRegionEnd;
+ /// Maps vregs to the SUnits of their uses in the current scheduling region.
+ VReg2SUnitMultiMap VRegUses;
+
// Map each SU to its summary of pressure changes. This array is updated for
// liveness during bottom-up scheduling. Top-down scheduling may proceed but
// has no affect on the pressure diffs.
@@ -491,6 +494,8 @@ protected:
void updateScheduledPressure(const SUnit *SU,
const std::vector<unsigned> &NewMaxPressure);
+
+ void collectVRegUses(SUnit &SU);
};
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h?rev=286654&r1=286653&r2=286654&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h Fri Nov 11 16:37:31 2016
@@ -138,11 +138,6 @@ namespace llvm {
/// scheduling region is mapped to an SUnit.
DenseMap<MachineInstr*, SUnit*> MISUnitMap;
- /// After calling BuildSchedGraph, each vreg used in the scheduling region
- /// is mapped to a set of SUnits. These include all local vreg uses, not
- /// just the uses for a singly defined vreg.
- VReg2SUnitMultiMap VRegUses;
-
/// State internal to DAG building.
/// -------------------------------
@@ -333,8 +328,6 @@ namespace llvm {
/// Returns a mask for which lanes get read/written by the given (register)
/// machine operand.
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
-
- void collectVRegUses(SUnit *SU);
};
/// newSUnit - Creates a new SUnit and return a ptr to it.
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=286654&r1=286653&r2=286654&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Nov 11 16:37:31 2016
@@ -865,6 +865,44 @@ ScheduleDAGMILive::~ScheduleDAGMILive()
delete DFSResult;
}
+void ScheduleDAGMILive::collectVRegUses(SUnit &SU) {
+ const MachineInstr &MI = *SU.getInstr();
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg())
+ continue;
+ if (!MO.readsReg())
+ continue;
+ if (TrackLaneMasks && !MO.isUse())
+ continue;
+
+ unsigned Reg = MO.getReg();
+ if (!TargetRegisterInfo::isVirtualRegister(Reg))
+ continue;
+
+ // Ignore re-defs.
+ if (TrackLaneMasks) {
+ bool FoundDef = false;
+ for (const MachineOperand &MO2 : MI.operands()) {
+ if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
+ FoundDef = true;
+ break;
+ }
+ }
+ if (FoundDef)
+ continue;
+ }
+
+ // Record this local VReg use.
+ VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
+ for (; UI != VRegUses.end(); ++UI) {
+ if (UI->SU == &SU)
+ break;
+ }
+ if (UI == VRegUses.end())
+ VRegUses.insert(VReg2SUnit(Reg, 0, &SU));
+ }
+}
+
/// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
/// crossing a scheduling boundary. [begin, end) includes all instructions in
/// the region, including the boundary itself and single-instruction regions
@@ -892,6 +930,11 @@ void ScheduleDAGMILive::enterRegion(Mach
// Setup the register pressure trackers for the top scheduled top and bottom
// scheduled regions.
void ScheduleDAGMILive::initRegPressure() {
+ VRegUses.clear();
+ VRegUses.setUniverse(MRI.getNumVirtRegs());
+ for (SUnit &SU : SUnits)
+ collectVRegUses(SU);
+
TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin,
ShouldTrackLaneMasks, false);
BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=286654&r1=286653&r2=286654&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Fri Nov 11 16:37:31 2016
@@ -680,44 +680,6 @@ void ScheduleDAGInstrs::initSUnits() {
}
}
-void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) {
- const MachineInstr *MI = SU->getInstr();
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg())
- continue;
- if (!MO.readsReg())
- continue;
- if (TrackLaneMasks && !MO.isUse())
- continue;
-
- unsigned Reg = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(Reg))
- continue;
-
- // Ignore re-defs.
- if (TrackLaneMasks) {
- bool FoundDef = false;
- for (const MachineOperand &MO2 : MI->operands()) {
- if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
- FoundDef = true;
- break;
- }
- }
- if (FoundDef)
- continue;
- }
-
- // Record this local VReg use.
- VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
- for (; UI != VRegUses.end(); ++UI) {
- if (UI->SU == SU)
- break;
- }
- if (UI == VRegUses.end())
- VRegUses.insert(VReg2SUnit(Reg, 0, SU));
- }
-}
-
class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
/// Current total number of SUs in map.
@@ -895,9 +857,6 @@ void ScheduleDAGInstrs::buildSchedGraph(
CurrentVRegDefs.setUniverse(NumVirtRegs);
CurrentVRegUses.setUniverse(NumVirtRegs);
- VRegUses.clear();
- VRegUses.setUniverse(NumVirtRegs);
-
// Model data dependencies between instructions being scheduled and the
// ExitSU.
addSchedBarrierDeps();
@@ -920,8 +879,6 @@ void ScheduleDAGInstrs::buildSchedGraph(
assert(SU && "No SUnit mapped to this MI");
if (RPTracker) {
- collectVRegUses(SU);
-
RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {
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