[llvm] r286619 - [InstCombine] add tests to show size-increasing select transforms

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Nov 11 13:37:54 2016
New Revision: 286619

URL: http://llvm.org/viewvc/llvm-project?rev=286619&view=rev
Log:
[InstCombine] add tests to show size-increasing select transforms

Modified:
    llvm/trunk/test/Transforms/InstCombine/select-bitext.ll

Modified: llvm/trunk/test/Transforms/InstCombine/select-bitext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-bitext.ll?rev=286619&r1=286618&r2=286619&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-bitext.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/select-bitext.ll Fri Nov 11 13:37:54 2016
@@ -1,6 +1,52 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+; FIXME: We should not grow the size of the select in the next 4 cases.
+
+define i64 @sel_sext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @sel_sext(
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 %a to i64
+; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    ret i64 [[EXT]]
+;
+  %sel = select i1 %cmp, i32 %a, i32 42
+  %ext = sext i32 %sel to i64
+  ret i64 %ext
+}
+
+define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) {
+; CHECK-LABEL: @sel_sext_vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = sext <4 x i32> %a to <4 x i64>
+; CHECK-NEXT:    [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT:    ret <4 x i64> [[EXT]]
+;
+  %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+  %ext = sext <4 x i32> %sel to <4 x i64>
+  ret <4 x i64> %ext
+}
+
+define i64 @sel_zext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @sel_zext(
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 %a to i64
+; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    ret i64 [[EXT]]
+;
+  %sel = select i1 %cmp, i32 %a, i32 42
+  %ext = zext i32 %sel to i64
+  ret i64 %ext
+}
+
+define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
+; CHECK-LABEL: @sel_zext_vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = zext <4 x i32> %a to <4 x i64>
+; CHECK-NEXT:    [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT:    ret <4 x i64> [[EXT]]
+;
+  %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+  %ext = zext <4 x i32> %sel to <4 x i64>
+  ret <4 x i64> %ext
+}
+
 define i32 @test_sext1(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_sext1(
 ; CHECK-NEXT:    [[FOLD_R:%.*]] = and i1 %ccb, %cca