[llvm] r286596 - [PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 11 06:41:19 PST 2016
Author: nemanjai
Date: Fri Nov 11 08:41:19 2016
New Revision: 286596
URL: http://llvm.org/viewvc/llvm-project?rev=286596&view=rev
Log:
[PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
This patch corresponds to review:
https://reviews.llvm.org/D26307
Adds all the intrinsics used for various conversion builtins that will
be added to altivec.h. These are type conversions between various types of
vectors.
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td?rev=286596&r1=286595&r2=286596&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td Fri Nov 11 08:41:19 2016
@@ -806,6 +806,30 @@ def int_ppc_vsx_xviexpdp :
def int_ppc_vsx_xviexpsp :
PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
[llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
+def int_ppc_vsx_xvcvdpsxws :
+ PowerPC_VSX_Intrinsic<"xvcvdpsxws", [llvm_v4i32_ty],
+ [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvdpuxws :
+ PowerPC_VSX_Intrinsic<"xvcvdpuxws", [llvm_v4i32_ty],
+ [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvsxwdp :
+ PowerPC_VSX_Intrinsic<"xvcvsxwdp", [llvm_v2f64_ty],
+ [llvm_v4i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvuxwdp :
+ PowerPC_VSX_Intrinsic<"xvcvuxwdp", [llvm_v2f64_ty],
+ [llvm_v4i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvspdp :
+ PowerPC_VSX_Intrinsic<"xvcvspdp", [llvm_v2f64_ty],
+ [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvsxdsp :
+ PowerPC_VSX_Intrinsic<"xvcvsxdsp", [llvm_v4f32_ty],
+ [llvm_v2i64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvuxdsp :
+ PowerPC_VSX_Intrinsic<"xvcvuxdsp", [llvm_v4f32_ty],
+ [llvm_v2i64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvdpsp :
+ PowerPC_VSX_Intrinsic<"xvcvdpsp", [llvm_v4f32_ty],
+ [llvm_v2f64_ty], [IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=286596&r1=286595&r2=286596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Fri Nov 11 08:41:19 2016
@@ -596,25 +596,29 @@ let Uses = [RM] in {
def XVCVDPSP : XX2Form<60, 393,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvdpsp $XT, $XB", IIC_VecFP, []>;
+ "xvcvdpsp $XT, $XB", IIC_VecFP,
+ [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
def XVCVDPSXDS : XX2Form<60, 472,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpsxds $XT, $XB", IIC_VecFP,
[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
def XVCVDPSXWS : XX2Form<60, 216,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
+ "xvcvdpsxws $XT, $XB", IIC_VecFP,
+ [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
def XVCVDPUXDS : XX2Form<60, 456,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpuxds $XT, $XB", IIC_VecFP,
[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
def XVCVDPUXWS : XX2Form<60, 200,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
+ "xvcvdpuxws $XT, $XB", IIC_VecFP,
+ [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
def XVCVSPDP : XX2Form<60, 457,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvspdp $XT, $XB", IIC_VecFP, []>;
+ "xvcvspdp $XT, $XB", IIC_VecFP,
+ [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
def XVCVSPSXDS : XX2Form<60, 408,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
@@ -633,10 +637,12 @@ let Uses = [RM] in {
[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
def XVCVSXDSP : XX2Form<60, 440,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
+ "xvcvsxdsp $XT, $XB", IIC_VecFP,
+ [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
def XVCVSXWDP : XX2Form<60, 248,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
+ "xvcvsxwdp $XT, $XB", IIC_VecFP,
+ [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
def XVCVSXWSP : XX2Form<60, 184,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvsxwsp $XT, $XB", IIC_VecFP,
@@ -647,10 +653,12 @@ let Uses = [RM] in {
[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
def XVCVUXDSP : XX2Form<60, 424,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
+ "xvcvuxdsp $XT, $XB", IIC_VecFP,
+ [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
def XVCVUXWDP : XX2Form<60, 232,
(outs vsrc:$XT), (ins vsrc:$XB),
- "xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
+ "xvcvuxwdp $XT, $XB", IIC_VecFP,
+ [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
def XVCVUXWSP : XX2Form<60, 168,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
Modified: llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll?rev=286596&r1=286595&r2=286596&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll Fri Nov 11 08:41:19 2016
@@ -159,6 +159,80 @@ entry:
}
; Function Attrs: nounwind readnone
+define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)
+ ret <4 x i32> %0
+; CHECK-LABEL: @emit_xvcvdpsxws
+; CHECK: xvcvdpsxws 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)
+ ret <4 x i32> %0
+; CHECK-LABEL: @emit_xvcvdpuxws
+; CHECK: xvcvdpuxws 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {
+entry:
+ %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)
+ ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvsxwdp
+; CHECK: xvcvsxwdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {
+entry:
+ %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)
+ ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvuxwdp
+; CHECK: xvcvuxwdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvspdp(<4 x float> %a) {
+entry:
+ %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)
+ ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvspdp
+; CHECK: xvcvspdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {
+entry:
+ %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)
+ ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvsxdsp
+; CHECK: xvcvsxdsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {
+entry:
+ %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)
+ ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvuxdsp
+; CHECK: xvcvuxdsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {
+entry:
+ %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)
+ ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvdpsp
+; CHECK: xvcvdpsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+
+; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
; Function Attrs: nounwind readnone
@@ -193,3 +267,11 @@ declare <2 x i64> @llvm.ppc.vsx.xvcmpgtd
; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
+declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
+declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1
+declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
+declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1
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