[llvm] r286509 - [SelectionDAG] Add support for splatted vectors in SUB opcode

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Nov 10 15:57:42 2016
New Revision: 286509

URL: http://llvm.org/viewvc/llvm-project?rev=286509&view=rev
Log:
[SelectionDAG] Add support for splatted vectors in SUB opcode

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=286509&r1=286508&r2=286509&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 10 15:57:42 2016
@@ -2414,7 +2414,7 @@ void SelectionDAG::computeKnownBits(SDVa
     break;
 
   case ISD::SUB: {
-    if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
+    if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
       // than C (i.e. no wrap-around can happen).  For example, 20-X is
       // positive if we can prove that X is >= 0 and < 16.

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=286509&r1=286508&r2=286509&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Thu Nov 10 15:57:42 2016
@@ -207,18 +207,12 @@ define <4 x i32> @knownbits_mask_trunc_s
 define <4 x i32> @knownbits_sub_lshr(<4 x i32> %a0) nounwind {
 ; X32-LABEL: knownbits_sub_lshr:
 ; X32:       # BB#0:
-; X32-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
-; X32-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
-; X32-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: knownbits_sub_lshr:
 ; X64:       # BB#0:
-; X64-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
-; X64-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
-; X64-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X64-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    retq
   %1 = and <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
   %2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1