[llvm] r286481 - [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Nov 10 11:43:52 2016
New Revision: 286481

URL: http://llvm.org/viewvc/llvm-project?rev=286481&view=rev
Log:
[SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=286481&r1=286480&r2=286481&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 10 11:43:52 2016
@@ -2394,7 +2394,8 @@ void SelectionDAG::computeKnownBits(SDVa
     unsigned InBits = InVT.getScalarSizeInBits();
     KnownZero = KnownZero.zext(InBits);
     KnownOne = KnownOne.zext(InBits);
-    computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
+    computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
+                     Depth + 1);
     KnownZero = KnownZero.trunc(BitWidth);
     KnownOne = KnownOne.trunc(BitWidth);
     break;

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=286481&r1=286480&r2=286481&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Thu Nov 10 11:43:52 2016
@@ -190,22 +190,12 @@ define <4 x i32> @knownbits_mask_mul_shu
 define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {
 ; X32-LABEL: knownbits_mask_trunc_shuffle_shl:
 ; X32:       # BB#0:
-; X32-NEXT:    vandps {{\.LCPI.*}}, %ymm0, %ymm0
-; X32-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; X32-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
-; X32-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X32-NEXT:    vpslld $22, %xmm0, %xmm0
-; X32-NEXT:    vzeroupper
+; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: knownbits_mask_trunc_shuffle_shl:
 ; X64:       # BB#0:
-; X64-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
-; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
-; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X64-NEXT:    vpslld $22, %xmm0, %xmm0
-; X64-NEXT:    vzeroupper
+; X64-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    retq
   %1 = and <4 x i64> %a0, <i64 -65536, i64 -7, i64 7, i64 -65536>
   %2 = trunc <4 x i64> %1 to <4 x i32>