[PATCH] D26181: RegCall - Handling v64i1 in 32/64 bit target

[Elena Demikhovsky via llvm-commits]

delena added inline comments.


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Comment at: lib/Target/X86/X86CallingConv.h:27
+/// The value should be assigned to two GPRs.
+inline bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT,
+                                          MVT &LocVT,
----------------
This function is too big to be inline. Can you move it to .c** file?


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Comment at: lib/Target/X86/X86CallingConv.h:34
+  // See also the regcall calling convention ABI for the full list of possible
+  // registers for mask types
+  static const std::vector<MCPhysReg> RegList{X86::EAX, X86::ECX, X86::EDX,
----------------
dot at the end of the sentence.


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Comment at: lib/Target/X86/X86CallingConv.h:35
+  // registers for mask types
+  static const std::vector<MCPhysReg> RegList{X86::EAX, X86::ECX, X86::EDX,
+                                              X86::EDI, X86::ESI};
----------------
What is this list for?


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Comment at: lib/Target/X86/X86CallingConv.h:39
+  // The vector will save all the available registers for allocation
+  std::vector<unsigned> availableRegs;
+
----------------
std::vector is not "popular" in the LLVM code. SmallVector can be used instead.


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Comment at: lib/Target/X86/X86CallingConv.h:50
+
+  unsigned remainingRegs = 2;
+
----------------
Why 2 ? Please add comments here.


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Comment at: lib/Target/X86/X86CallingConv.h:53
+  // Allocating the available registers
+  for (std::vector<unsigned>::iterator it = availableRegs.begin(),
+                                       end = availableRegs.end();
----------------
Does this loop allays have 2 iterations?


Repository:
  rL LLVM

https://reviews.llvm.org/D26181