[PATCH] D26305: [Power9] vector load/store with length - llvm portion

[Nemanja Ivanovic via llvm-commits]

nemanjai requested changes to this revision.
nemanjai added inline comments.
This revision now requires changes to proceed.


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Comment at: include/llvm/IR/IntrinsicsPowerPC.td:724
       Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvl :
+      Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem,
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I realized after we spoke yesterday that we have to change this. The length operand is in bits 0-7 of the second GPR operand. It therefore means that we cannot model this with an i32 so the instructions operands need to be G8RC and this has to be llvm_i64_ty.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2298
   // Load Vector (Left-justified) with Length
-  def LXVL    : X_XT6_RA5_RB5<31, 269, "lxvl"   , vsrc, []>;
-  def LXVLL   : X_XT6_RA5_RB5<31, 301, "lxvll"  , vsrc, []>;
+  def LXVL : XX1Form<31, 269, (outs vsrc:$XT), (ins memr:$src, gprc:$rB),
+                   "lxvl $XT, $src, $rB", IIC_LdStLoad,
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See comment above.


https://reviews.llvm.org/D26305