[llvm] r285732 - [InstCombine] allow splat vector folds in adjustMinMax()
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 7 08:08:43 PST 2016
Thanks, Greg. Looks like a simple failure to account for a scalar select
with vector operands.
I updated the patch with an extra check and test case:
https://reviews.llvm.org/rL286113
On Wed, Nov 2, 2016 at 6:21 PM, Greg Bedwell <gregbedwell at gmail.com> wrote:
> Hi Sanjay,
>
> I reverted in r285866. Thanks!
> See you tomorrow :)
>
> On 2 November 2016 at 21:15, Sanjay Patel <spatel at rotateright.com> wrote:
>
>> Thanks, Greg. I'm on my way to the dev mtg, so I probably can't debug
>> this until next week. Can you please revert the commit?
>>
>>
>> On Wednesday, November 2, 2016, Greg Bedwell <gregbedwell at gmail.com>
>> wrote:
>>
>>> Hi Sanjay,
>>>
>>> We've tracked a new assertion failure in our internal test suite to this
>>> commit. I've attached an ll file (generated from the following C++ source):
>>>
>>> // ================
>>> typedef short __v8hi __attribute__((__vector_size__(16)));
>>> __v8hi foo(__v8hi &V1, __v8hi &V2, unsigned mask) {
>>> __v8hi Result = V1;
>>> if (mask & 0x80)
>>> Result[0] = V2[0];
>>> return Result;
>>> }
>>> // ================
>>>
>>> opt 1.ll -O2 -o foo
>>> opt: /home/llvm-upstream/llvm/lib/IR/Constants.cpp:1583: static
>>> llvm::Constant* llvm::ConstantExpr::getSExt(llvm::Constant*,
>>> llvm::Type*, bool): Assertion `(fromVec == toVec) && "Cannot convert from
>>> scalar to/from vector"' failed.
>>>
>>> -Greg
>>>
>>> On 1 November 2016 at 20:08, Sanjay Patel via llvm-commits <
>>> llvm-commits at lists.llvm.org> wrote:
>>>
>>>> Author: spatel
>>>> Date: Tue Nov 1 15:08:02 2016
>>>> New Revision: 285732
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=285732&view=rev
>>>> Log:
>>>> [InstCombine] allow splat vector folds in adjustMinMax()
>>>>
>>>> Modified:
>>>> llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
>>>> llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll
>>>>
>>>> Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transform
>>>> s/InstCombine/InstCombineSelect.cpp?rev=285732&r1=285731&r2=
>>>> 285732&view=diff
>>>> ============================================================
>>>> ==================
>>>> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Tue
>>>> Nov 1 15:08:02 2016
>>>> @@ -424,24 +424,20 @@ static bool adjustMinMax(SelectInst &Sel
>>>> Value *FalseVal = Sel.getFalseValue();
>>>>
>>>> // We may move or edit the compare, so make sure the select is the
>>>> only user.
>>>> - if (!Cmp.hasOneUse())
>>>> + const APInt *CmpC;
>>>> + if (!Cmp.hasOneUse() || !match(CmpRHS, m_APInt(CmpC)))
>>>> return false;
>>>>
>>>> - // FIXME: Use m_APInt to allow vector folds.
>>>> - auto *CI = dyn_cast<ConstantInt>(CmpRHS);
>>>> - if (!CI)
>>>> - return false;
>>>> -
>>>> - // These transformations only work for selects over integers.
>>>> - IntegerType *SelectTy = dyn_cast<IntegerType>(Sel.getType());
>>>> - if (!SelectTy)
>>>> + // These transforms only work for selects of integers or vector
>>>> integers.
>>>> + auto *SelEltTy = dyn_cast<IntegerType>(Sel.getT
>>>> ype()->getScalarType());
>>>> + if (!SelEltTy)
>>>> return false;
>>>>
>>>> Constant *AdjustedRHS;
>>>> if (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_SGT)
>>>> - AdjustedRHS = ConstantInt::get(CI->getContext(), CI->getValue() +
>>>> 1);
>>>> + AdjustedRHS = ConstantInt::get(CmpRHS->getType(), *CmpC + 1);
>>>> else if (Pred == ICmpInst::ICMP_ULT || Pred == ICmpInst::ICMP_SLT)
>>>> - AdjustedRHS = ConstantInt::get(CI->getContext(), CI->getValue() -
>>>> 1);
>>>> + AdjustedRHS = ConstantInt::get(CmpRHS->getType(), *CmpC - 1);
>>>> else
>>>> return false;
>>>>
>>>> @@ -454,8 +450,8 @@ static bool adjustMinMax(SelectInst &Sel
>>>> // Types do not match. Instead of calculating this with mixed types,
>>>> promote
>>>> // all to the larger type. This enables scalar evolution to analyze
>>>> this
>>>> // expression.
>>>> - else if (CmpRHS->getType()->getScalarSizeInBits() <
>>>> SelectTy->getBitWidth()) {
>>>> - Constant *SextRHS = ConstantExpr::getSExt(AdjustedRHS, SelectTy);
>>>> + else if (CmpRHS->getType()->getScalarSizeInBits() <
>>>> SelEltTy->getBitWidth()) {
>>>> + Constant *SextRHS = ConstantExpr::getSExt(AdjustedRHS,
>>>> Sel.getType());
>>>>
>>>> // X = sext x; x >s c ? X : C+1 --> X = sext x; X <s C+1 ? C+1 : X
>>>> // X = sext x; x <s c ? X : C-1 --> X = sext x; X >s C-1 ? C-1 : X
>>>> @@ -469,7 +465,7 @@ static bool adjustMinMax(SelectInst &Sel
>>>> CmpLHS = FalseVal;
>>>> AdjustedRHS = SextRHS;
>>>> } else if (Cmp.isUnsigned()) {
>>>> - Constant *ZextRHS = ConstantExpr::getZExt(AdjustedRHS,
>>>> SelectTy);
>>>> + Constant *ZextRHS = ConstantExpr::getZExt(AdjustedRHS,
>>>> Sel.getType());
>>>> // X = zext x; x >u c ? X : C+1 --> X = zext x; X <u C+1 ? C+1 :
>>>> X
>>>> // X = zext x; x <u c ? X : C-1 --> X = zext x; X >u C-1 ? C-1 :
>>>> X
>>>> // zext + signed compare cannot be changed:
>>>>
>>>> Modified: llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transfor
>>>> ms/InstCombine/adjust-for-minmax.ll?rev=285732&r1=285731&r2=
>>>> 285732&view=diff
>>>> ============================================================
>>>> ==================
>>>> --- llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll
>>>> (original)
>>>> +++ llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll Tue
>>>> Nov 1 15:08:02 2016
>>>> @@ -68,13 +68,12 @@ define i32 @smax3(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Swap vector signed pred and select ops.
>>>>
>>>> define <2 x i32> @smax3_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @smax3_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> zeroinitializer
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32>
>>>> zeroinitializer, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
>>>> @@ -95,13 +94,12 @@ define i32 @smin3(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Swap vector signed pred and select ops.
>>>>
>>>> define <2 x i32> @smin3_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @smin3_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> zeroinitializer
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32>
>>>> zeroinitializer, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp slt <2 x i32> %n, <i32 1, i32 1>
>>>> @@ -122,13 +120,12 @@ define i32 @umax3(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Swap vector unsigned pred and select ops.
>>>>
>>>> define <2 x i32> @umax3_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @umax3_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 4, i32 4>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> <i32 5, i32 5>
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 5, i32 5>
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 5,
>>>> i32 5>, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
>>>> @@ -149,13 +146,12 @@ define i32 @umin3(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Swap vector unsigned pred and select ops.
>>>>
>>>> define <2 x i32> @umin3_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @umin3_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 7, i32 7>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> <i32 6, i32 6>
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 6, i32 6>
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 6,
>>>> i32 6>, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp ult <2 x i32> %n, <i32 7, i32 7>
>>>> @@ -176,13 +172,12 @@ define i32 @smax4(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Canonicalize vector signed pred and swap pred and select ops.
>>>>
>>>> define <2 x i32> @smax4_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @smax4_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> zeroinitializer
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32>
>>>> zeroinitializer, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp sge <2 x i32> %n, zeroinitializer
>>>> @@ -203,13 +198,12 @@ define i32 @smin4(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Canonicalize vector signed pred and swap pred and select ops.
>>>>
>>>> define <2 x i32> @smin4_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @smin4_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> zeroinitializer
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32>
>>>> zeroinitializer, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp sle <2 x i32> %n, zeroinitializer
>>>> @@ -230,13 +224,12 @@ define i32 @umax4(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Canonicalize vector unsigned pred and swap pred and select ops.
>>>>
>>>> define <2 x i32> @umax4_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @umax4_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 7, i32 7>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> <i32 8, i32 8>
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 8, i32 8>
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 8,
>>>> i32 8>, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp uge <2 x i32> %n, <i32 8, i32 8>
>>>> @@ -257,13 +250,12 @@ define i32 @umin4(i32 %n) {
>>>> ret i32 %m
>>>> }
>>>>
>>>> -; FIXME
>>>> ; Canonicalize vector unsigned pred and swap pred and select ops.
>>>>
>>>> define <2 x i32> @umin4_vec(<2 x i32> %n) {
>>>> ; CHECK-LABEL: @umin4_vec(
>>>> -; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 10, i32 10>
>>>> -; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x
>>>> i32> <i32 9, i32 9>
>>>> +; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 9, i32 9>
>>>> +; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 9,
>>>> i32 9>, <2 x i32> %n
>>>> ; CHECK-NEXT: ret <2 x i32> [[M]]
>>>> ;
>>>> %t = icmp ule <2 x i32> %n, <i32 9, i32 9>
>>>> @@ -284,12 +276,11 @@ define i64 @smax_sext(i32 %a) {
>>>> ret i64 %max
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @smax_sext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
>>>> -; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> zeroinitializer
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i64> [[A_EXT]],
>>>> zeroinitializer
>>>> +; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> zeroinitializer, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MAX]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -311,12 +302,11 @@ define i64 @smin_sext(i32 %a) {
>>>> ret i64 %min
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @smin_sext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %a, <i32 1, i32 1>
>>>> -; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> zeroinitializer
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i64> [[A_EXT]],
>>>> zeroinitializer
>>>> +; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> zeroinitializer, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MIN]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -338,12 +328,11 @@ define i64 @umax_sext(i32 %a) {
>>>> ret i64 %max
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umax_sext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
>>>> -; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 3, i64 3>
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3,
>>>> i64 3>
>>>> +; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 3, i64 3>, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MAX]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -365,12 +354,11 @@ define i64 @umin_sext(i32 %a) {
>>>> ret i64 %min
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umin_sext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
>>>> -; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 2, i64 2>
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2,
>>>> i64 2>
>>>> +; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 2, i64 2>, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MIN]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -392,12 +380,11 @@ define i64 @umax_sext2(i32 %a) {
>>>> ret i64 %min
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umax_sext2_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
>>>> -; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 2, i64 2>, <2 x i64> [[A_EXT]]
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2,
>>>> i64 2>
>>>> +; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 2, i64 2>
>>>> ; CHECK-NEXT: ret <2 x i64> [[MIN]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -419,12 +406,11 @@ define i64 @umin_sext2(i32 %a) {
>>>> ret i64 %min
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umin_sext2_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
>>>> -; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 3, i64 3>, <2 x i64> [[A_EXT]]
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3,
>>>> i64 3>
>>>> +; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 3, i64 3>
>>>> ; CHECK-NEXT: ret <2 x i64> [[MIN]]
>>>> ;
>>>> %a_ext = sext <2 x i32> %a to <2 x i64>
>>>> @@ -446,12 +432,11 @@ define i64 @umax_zext(i32 %a) {
>>>> ret i64 %max
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umax_zext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
>>>> -; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 3, i64 3>
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3,
>>>> i64 3>
>>>> +; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 3, i64 3>, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MAX]]
>>>> ;
>>>> %a_ext = zext <2 x i32> %a to <2 x i64>
>>>> @@ -473,12 +458,11 @@ define i64 @umin_zext(i32 %a) {
>>>> ret i64 %min
>>>> }
>>>>
>>>> -; FIXME
>>>> define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
>>>> ; CHECK-LABEL: @umin_zext_vec(
>>>> ; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
>>>> -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
>>>> -; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64>
>>>> [[A_EXT]], <2 x i64> <i64 2, i64 2>
>>>> +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2,
>>>> i64 2>
>>>> +; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64
>>>> 2, i64 2>, <2 x i64> [[A_EXT]]
>>>> ; CHECK-NEXT: ret <2 x i64> [[MIN]]
>>>> ;
>>>> %a_ext = zext <2 x i32> %a to <2 x i64>
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at lists.llvm.org
>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>>>
>>>
>>>
>
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