[PATCH] D26313: [AArch64] Transfer memory operands when lowering vector load and store intrinsics

[Sanjin Sijaric via llvm-commits]

ssijaric created this revision.
ssijaric added reviewers: mcrosier, jmolloy, t.p.northover.
ssijaric added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

Some vector loads and stores generated from AArch64 intrinsics alias each other unnecessarily, preventing better scheduling.  We just need to transfer memory operands during lowering.


https://reviews.llvm.org/D26313

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/arm64-misched-basic-A53.ll
  test/CodeGen/AArch64/sched-past-vector-ldst.ll

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