[PATCH] D25551: AMDGPU: Implement SGPR spilling with scalar stores

[Nicolai Hähnle via llvm-commits]

nhaehnle added a comment.

One question about the offsets at which spills happen, though this could stay a TODO for now. Apart from that, LGTM.



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Comment at: test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll:27-37
+; SMEM: s_mov_b32 m0, s97{{$}}
+; SMEM: s_buffer_load_dword s{{[0-9]+}}, s[92:95], m0 ; 16-byte Folded Reload
+; SMEM: s_add_u32 m0, s97, 0x100{{$}}
+; SMEM: s_waitcnt lgkmcnt(0)
+; SMEM: s_buffer_load_dword s{{[0-9]+}}, s[92:95], m0 ; 16-byte Folded Reload
+; SMEM: s_add_u32 m0, s97, 0x200{{$}}
+; SMEM: s_waitcnt lgkmcnt(0)
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I'm a bit surprised by the offsets as they seem too far apart. I guess the offset allocation assumes VGPR spilling, and this is a TODO to be fixed later? Should probably be mentioned here in the test and in the appropriate location in the code.


https://reviews.llvm.org/D25551