[PATCH] D25656: AMDGPU: Allow additional implicit operands on MOVRELS instructions

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL285835: AMDGPU: Allow additional implicit operands on MOVRELS instructions (authored by nha).

Changed prior to commit:
  https://reviews.llvm.org/D25656?vs=75580&id=76730#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25656

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir


Index: llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir
@@ -0,0 +1,31 @@
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched  %s -o - | FileCheck %s
+
+# This tests a situation where a sub-register of a killed super-register operand
+# of V_MOVRELS happens to have an undef use later on. This leads to the post RA
+# scheduler adding additional implicit operands to the V_MOVRELS, which used
+# to fail machine instruction verification.
+
+--- |
+
+  define amdgpu_vs void @main(i32 %arg) { ret void }
+
+...
+---
+# CHECK-LABEL: name: main
+# CHECK-LABEL: bb.0:
+# CHECK: V_MOVRELS_B32_e32
+# CHECK: V_MAC_F32_e32
+
+name:            main
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %m0 = S_MOV_B32 undef %sgpr0
+    V_MOVRELD_B32_e32 undef %vgpr2, 0, implicit %m0, implicit %exec, implicit-def %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
+    %m0 = S_MOV_B32 undef %sgpr0
+    %vgpr1 = V_MOVRELS_B32_e32 undef %vgpr1, implicit %m0, implicit %exec, implicit killed %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+    %vgpr4 = V_MAC_F32_e32 undef %vgpr0, undef %vgpr0, undef %vgpr4, implicit %exec
+    EXP 15, 12, 0, 1, 0, undef %vgpr0, killed %vgpr1, killed %vgpr4, undef %vgpr0, implicit %exec
+    S_ENDPGM
+
+...
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2101,7 +2101,10 @@
       Desc.getNumImplicitUses();
     const unsigned NumImplicitOps = IsDst ? 2 : 1;
 
-    if (MI.getNumOperands() != StaticNumOps + NumImplicitOps) {
+    // Allow additional implicit operands. This allows a fixup done by the post
+    // RA scheduler where the main implicit operand is killed and implicit-defs
+    // are added for sub-registers that remain live after this instruction.
+    if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
       ErrInfo = "missing implicit register operands";
       return false;
     }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D25656.76730.patch
Type: text/x-patch
Size: 2298 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20161102/43dfa1de/attachment.bin>