[lld] r285719 - Implement R_PPC_REL24 and R_PPC_REL32 relocations.

[Rui Ueyama via llvm-commits]

Author: ruiu
Date: Tue Nov  1 13:30:26 2016
New Revision: 285719

URL: http://llvm.org/viewvc/llvm-project?rev=285719&view=rev
Log:
Implement R_PPC_REL24 and R_PPC_REL32 relocations.

This enables LLD to relocate PC-relative R_PPC_REL32 and
R_PPC_REL24 types (as used in bl instructions).

Patch from Jack Andersen!

Modified:
    lld/trunk/ELF/Target.cpp
    lld/trunk/test/ELF/ppc-relocs.s

Modified: lld/trunk/ELF/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Target.cpp?rev=285719&r1=285718&r2=285719&view=diff
==============================================================================
--- lld/trunk/ELF/Target.cpp (original)
+++ lld/trunk/ELF/Target.cpp Tue Nov  1 13:30:26 2016
@@ -47,6 +47,7 @@ namespace elf {
 TargetInfo *Target;
 
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
 
 StringRef getRelName(uint32_t Type) {
   return getELFRelocationTypeName(Config->EMachine, Type);
@@ -965,13 +966,25 @@ void PPCTargetInfo::relocateOne(uint8_t
   case R_PPC_ADDR16_LO:
     write16be(Loc, applyPPCLo(Val));
     break;
+  case R_PPC_REL24:
+    or32be(Loc, Val & 0x3FFFFFC);
+    break;
+  case R_PPC_REL32:
+    write32be(Loc, Val);
+    break;
   default:
     fatal("unrecognized reloc " + Twine(Type));
   }
 }
 
 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
-  return R_ABS;
+  switch (Type) {
+  case R_PPC_REL24:
+  case R_PPC_REL32:
+    return R_PC;
+  default:
+    return R_ABS;
+  }
 }
 
 PPC64TargetInfo::PPC64TargetInfo() {

Modified: lld/trunk/test/ELF/ppc-relocs.s
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/ppc-relocs.s?rev=285719&r1=285718&r2=285719&view=diff
==============================================================================
--- lld/trunk/test/ELF/ppc-relocs.s (original)
+++ lld/trunk/test/ELF/ppc-relocs.s Tue Nov  1 13:30:26 2016
@@ -28,3 +28,26 @@ mystr:
 # CHECK:    11008:       38 84 10 04     addi 4, 4, 4100
 # CHECK: mystr:
 # CHECK:    1100c:       62 6c 61 68     ori 12, 19, 24936
+
+.align  2
+.section .R_PPC_REL24,"ax", at progbits
+.globl .FR_PPC_REL24
+.FR_PPC_REL24:
+  b .Lfoox
+.section .R_PPC_REL24_2,"ax", at progbits
+.Lfoox:
+
+# CHECK: Disassembly of section .R_PPC_REL24:
+# CHECK: .FR_PPC_REL24:
+# CHECK:    11014:       48 00 00 04     b .+4
+
+.section .R_PPC_REL32,"ax", at progbits
+.globl .FR_PPC_REL32
+.FR_PPC_REL32:
+  .long .Lfoox3 - .
+.section .R_PPC_REL32_2,"ax", at progbits
+.Lfoox3:
+
+# CHECK: Disassembly of section .R_PPC_REL32:
+# CHECK: .FR_PPC_REL32:
+# CHECK:    11018:       00 00 00 04