[llvm] r285712 - [RISCV] Add stub backend
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 10:27:55 PDT 2016
Author: asb
Date: Tue Nov 1 12:27:54 2016
New Revision: 285712
URL: http://llvm.org/viewvc/llvm-project?rev=285712&view=rev
Log:
[RISCV] Add stub backend
This contains just enough for lib/Target/RISCV to compile. Notably a basic
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc
-march=riscv32 myinput.ll and will find it fails due to the lack of
MCAsmInfo.
See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for
further discussion
Differential Revision: https://reviews.llvm.org/D23560
Added:
llvm/trunk/lib/Target/RISCV/
llvm/trunk/lib/Target/RISCV/CMakeLists.txt
llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h
llvm/trunk/lib/Target/RISCV/TargetInfo/
llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt
llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt
llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
Modified:
llvm/trunk/CMakeLists.txt
llvm/trunk/CODE_OWNERS.TXT
llvm/trunk/docs/CompilerWriterInfo.rst
llvm/trunk/lib/Target/LLVMBuild.txt
Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=285712&r1=285711&r2=285712&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Tue Nov 1 12:27:54 2016
@@ -279,6 +279,7 @@ set(LLVM_ALL_TARGETS
MSP430
NVPTX
PowerPC
+ RISCV
Sparc
SystemZ
X86
Modified: llvm/trunk/CODE_OWNERS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CODE_OWNERS.TXT?rev=285712&r1=285711&r2=285712&view=diff
==============================================================================
--- llvm/trunk/CODE_OWNERS.TXT (original)
+++ llvm/trunk/CODE_OWNERS.TXT Tue Nov 1 12:27:54 2016
@@ -17,6 +17,10 @@ E: mail at justinbogner.com
D: InstrProfiling and related parts of ProfileData
D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
+N: Alex Bradbury
+E: asb at lowrisc.org
+D: RISC-V backend (lib/Target/RISCV/*)
+
N: Chandler Carruth
E: chandlerc at gmail.com
E: chandlerc at google.com
Modified: llvm/trunk/docs/CompilerWriterInfo.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerWriterInfo.rst?rev=285712&r1=285711&r2=285712&view=diff
==============================================================================
--- llvm/trunk/docs/CompilerWriterInfo.rst (original)
+++ llvm/trunk/docs/CompilerWriterInfo.rst Tue Nov 1 12:27:54 2016
@@ -83,6 +83,10 @@ AMDGPU
* `AMD Compute Resources <http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/>`_
* `AMDGPU Compute Application Binary Interface <https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md>`__
+RISC-V
+------
+* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_
+
SPARC
-----
Modified: llvm/trunk/lib/Target/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=285712&r1=285711&r2=285712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/LLVMBuild.txt Tue Nov 1 12:27:54 2016
@@ -30,6 +30,7 @@ subdirectories =
NVPTX
Mips
PowerPC
+ RISCV
Sparc
SystemZ
WebAssembly
Added: llvm/trunk/lib/Target/RISCV/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/CMakeLists.txt?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/CMakeLists.txt (added)
+++ llvm/trunk/lib/Target/RISCV/CMakeLists.txt Tue Nov 1 12:27:54 2016
@@ -0,0 +1,5 @@
+add_llvm_target(RISCVCodeGen
+ RISCVTargetMachine.cpp
+ )
+
+add_subdirectory(TargetInfo)
Added: llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/LLVMBuild.txt?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/LLVMBuild.txt (added)
+++ llvm/trunk/lib/Target/RISCV/LLVMBuild.txt Tue Nov 1 12:27:54 2016
@@ -0,0 +1,31 @@
+;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[common]
+subdirectories = TargetInfo
+
+[component_0]
+type = TargetGroup
+name = RISCV
+parent = Target
+
+[component_1]
+type = Library
+name = RISCVCodeGen
+parent = RISCV
+required_libraries = Core CodeGen RISCVInfo Support Target
+add_to_library_groups = RISCV
Added: llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp (added)
+++ llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp Tue Nov 1 12:27:54 2016
@@ -0,0 +1,58 @@
+//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Implements the info about RISCV target spec.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVTargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetOptions.h"
+using namespace llvm;
+
+extern "C" void LLVMInitializeRISCVTarget() {
+ RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
+ RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
+}
+
+static std::string computeDataLayout(const Triple &TT) {
+ if (TT.isArch64Bit()) {
+ return "e-m:e-i64:64-n32:64-S128";
+ } else {
+ assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
+ return "e-m:e-i64:64-n32-S128";
+ }
+}
+
+static Reloc::Model getEffectiveRelocModel(const Triple &TT,
+ Optional<Reloc::Model> RM) {
+ if (!RM.hasValue())
+ return Reloc::Static;
+ return *RM;
+}
+
+RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Optional<Reloc::Model> RM,
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
+ getEffectiveRelocModel(TT, RM), CM, OL),
+ TLOF(make_unique<TargetLoweringObjectFileELF>()) {}
+
+TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new TargetPassConfig(this, PM);
+}
Added: llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h (added)
+++ llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h Tue Nov 1 12:27:54 2016
@@ -0,0 +1,41 @@
+//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the RISCV specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
+#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/IR/DataLayout.h"
+
+namespace llvm {
+class RISCVTargetMachine : public LLVMTargetMachine {
+ std::unique_ptr<TargetLoweringObjectFile> TLOF;
+
+public:
+ RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+ StringRef FS, const TargetOptions &Options,
+ Optional<Reloc::Model> RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+ TargetLoweringObjectFile *getObjFileLowering() const override {
+ return TLOF.get();
+ }
+};
+Target &getTheRISCV32Target();
+Target &getTheRISCV64Target();
+}
+
+#endif
Added: llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt (added)
+++ llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt Tue Nov 1 12:27:54 2016
@@ -0,0 +1,3 @@
+add_llvm_library(LLVMRISCVInfo
+ RISCVTargetInfo.cpp
+ )
Added: llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt (added)
+++ llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt Tue Nov 1 12:27:54 2016
@@ -0,0 +1,23 @@
+;===- ./lib/Target/RISCV/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = RISCVInfo
+parent = RISCV
+required_libraries = Support
+add_to_library_groups = RISCV
Added: llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp?rev=285712&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp (added)
+++ llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp Tue Nov 1 12:27:54 2016
@@ -0,0 +1,35 @@
+//===-- RISCVTargetInfo.cpp - RISCV Target Implementation -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/TargetRegistry.h"
+using namespace llvm;
+
+namespace llvm {
+Target &getTheRISCV32Target() {
+ static Target TheRISCV32Target;
+ return TheRISCV32Target;
+}
+
+Target &getTheRISCV64Target() {
+ static Target TheRISCV64Target;
+ return TheRISCV64Target;
+}
+}
+
+extern "C" void LLVMInitializeRISCVTargetInfo() {
+ RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
+ "32-bit RISC-V");
+ RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
+ "64-bit RISC-V");
+}
+
+// FIXME: Temporary stub - this function must be defined for linking
+// to succeed and will be called unconditionally by llc, so must be a no-op.
+// Remove once this function is properly implemented.
+extern "C" void LLVMInitializeRISCVTargetMC() {}
More information about the llvm-commits
mailing list