[PATCH] D26120: [Cortex-M0] Atomic lowering
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 31 13:28:16 PDT 2016
efriedma requested changes to this revision.
efriedma added a reviewer: efriedma.
efriedma added a comment.
This revision now requires changes to proceed.
Explicitly checking isARMv6m() is wrong... we want to check features, not specific architectures. I think here, we're interested here in the behavior of targets with the following characteristics:
(1) Are in thumb mode (isThumb())
(2) Support a memory barrier instruction (hasAnyDataBarrier())
(3) Don't support ldrex/strex (!hasV8MBaselineOps())
I think ARMv6sm also has these characteristics; checking features makes the code more clear, and avoids mistakes.
It would also be a good idea to add tests to check that this patch doesn't change the generated code for other atomic operations.
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