[PATCH] D26120: [Cortex-M0] Atomic lowering

[Weiming Zhao via llvm-commits]

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ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls.


Repository:
  rL LLVM

https://reviews.llvm.org/D26120

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMSubtarget.cpp
  lib/Target/ARM/ARMSubtarget.h
  test/CodeGen/ARM/atomic-op.ll

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