[PATCH] D26104: AMDGPU: Use wider scalar spills for SGPR spilling
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 16:11:37 PDT 2016
arsenm created this revision.
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Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl, qcolombet.
Herald added a reviewer: tstellarAMD.
Since the spill is for the whole wave, these
don't have the swizzling problems that vector stores do
and a single 4-byte allocation is enough to spill a 64 element
register. This should reduce the number of spill instructions and
put all the spills for a register in the same cacheline.
This should save allocated private size, but for now it doesn't.
The extra slots are allocated for each component, but never used
because the frame layout is essentially finalized before frame
indices are replaced. For always using the scalar store path,
this should probably be moved into processFunctionBeforeFrameFinalized.
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