[llvm] r285417 - More swift calling convention tests
Arnold Schwaighofer via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 10:21:06 PDT 2016
Author: arnolds
Date: Fri Oct 28 12:21:05 2016
New Revision: 285417
URL: http://llvm.org/viewvc/llvm-project?rev=285417&view=rev
Log:
More swift calling convention tests
Added:
llvm/trunk/test/CodeGen/AArch64/swift-return.ll
Modified:
llvm/trunk/test/CodeGen/AArch64/swifterror.ll
llvm/trunk/test/CodeGen/ARM/swift-return.ll
llvm/trunk/test/CodeGen/ARM/swifterror.ll
llvm/trunk/test/CodeGen/X86/swift-return.ll
llvm/trunk/test/CodeGen/X86/swifterror.ll
Added: llvm/trunk/test/CodeGen/AArch64/swift-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swift-return.ll?rev=285417&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/swift-return.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/swift-return.ll Fri Oct 28 12:21:05 2016
@@ -0,0 +1,296 @@
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
+; RUN: llc -O0 -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-O0
+
+; CHECK-LABEL: test1
+; CHECK: bl _gen
+; CHECK: sxth [[TMP:w.*]], w0
+; CHECK: add w0, [[TMP]], w1, sxtb
+; CHECK-O0-LABEL: test1
+; CHECK-O0: bl _gen
+; CHECK-O0: sxth [[TMP:w.*]], w0
+; CHECK-O0: add w0, [[TMP]], w1, sxtb
+define i16 @test1(i32) {
+entry:
+ %call = call swiftcc { i16, i8 } @gen(i32 %0)
+ %v3 = extractvalue { i16, i8 } %call, 0
+ %v1 = sext i16 %v3 to i32
+ %v5 = extractvalue { i16, i8 } %call, 1
+ %v2 = sext i8 %v5 to i32
+ %add = add nsw i32 %v1, %v2
+ %conv = trunc i32 %add to i16
+ ret i16 %conv
+}
+
+declare swiftcc { i16, i8 } @gen(i32)
+
+; CHECK-LABEL: test2
+; CHECK: bl _gen2
+; CHECK: add [[TMP:x.*]], x0, x1
+; CHECK: add [[TMP]], [[TMP]], x2
+; CHECK: add [[TMP]], [[TMP]], x3
+; CHECK: add x0, [[TMP]], x4
+; CHECK-O0-LABEL: test2
+; CHECK-O0: bl _gen2
+; CHECK-O0: add [[TMP:x.*]], x0, x1
+; CHECK-O0: add [[TMP]], [[TMP]], x2
+; CHECK-O0: add [[TMP]], [[TMP]], x3
+; CHECK-O0: add x0, [[TMP]], x4
+
+define i64 @test2(i64 %key) {
+entry:
+ %key.addr = alloca i64, align 4
+ store i64 %key, i64* %key.addr, align 4
+ %0 = load i64, i64* %key.addr, align 4
+ %call = call swiftcc { i64, i64, i64, i64, i64 } @gen2(i64 %0)
+
+ %v3 = extractvalue { i64, i64, i64, i64, i64 } %call, 0
+ %v5 = extractvalue { i64, i64, i64, i64, i64 } %call, 1
+ %v6 = extractvalue { i64, i64, i64, i64, i64 } %call, 2
+ %v7 = extractvalue { i64, i64, i64, i64, i64 } %call, 3
+ %v8 = extractvalue { i64, i64, i64, i64, i64 } %call, 4
+
+ %add = add nsw i64 %v3, %v5
+ %add1 = add nsw i64 %add, %v6
+ %add2 = add nsw i64 %add1, %v7
+ %add3 = add nsw i64 %add2, %v8
+ ret i64 %add3
+}
+; CHECK-LABEL: gen2:
+; CHECK: mov x1, x0
+; CHECK: mov x2, x0
+; CHECK: mov x3, x0
+; CHECK: mov x4, x0
+; CHECK: ret
+define swiftcc { i64, i64, i64, i64, i64 } @gen2(i64 %key) {
+ %Y = insertvalue { i64, i64, i64, i64, i64 } undef, i64 %key, 0
+ %Z = insertvalue { i64, i64, i64, i64, i64 } %Y, i64 %key, 1
+ %Z2 = insertvalue { i64, i64, i64, i64, i64 } %Z, i64 %key, 2
+ %Z3 = insertvalue { i64, i64, i64, i64, i64 } %Z2, i64 %key, 3
+ %Z4 = insertvalue { i64, i64, i64, i64, i64 } %Z3, i64 %key, 4
+ ret { i64, i64, i64, i64, i64 } %Z4
+}
+
+; CHECK-LABEL: test3
+; CHECK: bl _gen3
+; CHECK: add [[TMP:w.*]], w0, w1
+; CHECK: add [[TMP]], [[TMP]], w2
+; CHECK: add w0, [[TMP]], w3
+; CHECK-O0-LABEL: test3
+; CHECK-O0: bl _gen3
+; CHECK-O0: add [[TMP:w.*]], w0, w1
+; CHECK-O0: add [[TMP]], [[TMP]], w2
+; CHECK-O0: add w0, [[TMP]], w3
+define i32 @test3(i32) {
+entry:
+ %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)
+
+ %v3 = extractvalue { i32, i32, i32, i32 } %call, 0
+ %v5 = extractvalue { i32, i32, i32, i32 } %call, 1
+ %v6 = extractvalue { i32, i32, i32, i32 } %call, 2
+ %v7 = extractvalue { i32, i32, i32, i32 } %call, 3
+
+ %add = add nsw i32 %v3, %v5
+ %add1 = add nsw i32 %add, %v6
+ %add2 = add nsw i32 %add1, %v7
+ ret i32 %add2
+}
+
+declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
+
+; CHECK-LABEL: test4
+; CHECK: bl _gen4
+; CHECK: fadd s0, s0, s1
+; CHECK: fadd s0, s0, s2
+; CHECK: fadd s0, s0, s3
+; CHECK-O0-LABEL: test4
+; CHECK-O0: bl _gen4
+; CHECK-O0: fadd s0, s0, s1
+; CHECK-O0: fadd s0, s0, s2
+; CHECK-O0: fadd s0, s0, s3
+define float @test4(float) {
+entry:
+ %call = call swiftcc { float, float, float, float } @gen4(float %0)
+
+ %v3 = extractvalue { float, float, float, float } %call, 0
+ %v5 = extractvalue { float, float, float, float } %call, 1
+ %v6 = extractvalue { float, float, float, float } %call, 2
+ %v7 = extractvalue { float, float, float, float } %call, 3
+
+ %add = fadd float %v3, %v5
+ %add1 = fadd float %add, %v6
+ %add2 = fadd float %add1, %v7
+ ret float %add2
+}
+
+declare swiftcc { float, float, float, float } @gen4(float %key)
+
+; CHECK-LABEL: test5
+; CHECK: bl _gen5
+; CHECK: fadd d0, d0, d1
+; CHECK: fadd d0, d0, d2
+; CHECK: fadd d0, d0, d3
+; CHECK-O0-LABEL: test5
+; CHECK-O0: bl _gen5
+; CHECK-O0: fadd d0, d0, d1
+; CHECK-O0: fadd d0, d0, d2
+; CHECK-O0: fadd d0, d0, d3
+define swiftcc double @test5(){
+entry:
+ %call = call swiftcc { double, double, double, double } @gen5()
+
+ %v3 = extractvalue { double, double, double, double } %call, 0
+ %v5 = extractvalue { double, double, double, double } %call, 1
+ %v6 = extractvalue { double, double, double, double } %call, 2
+ %v7 = extractvalue { double, double, double, double } %call, 3
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+ ret double %add2
+}
+
+declare swiftcc { double, double, double, double } @gen5()
+
+; CHECK-LABEL: test6
+; CHECK: bl _gen6
+; CHECK-DAG: fadd d0, d0, d1
+; CHECK-DAG: fadd d0, d0, d2
+; CHECK-DAG: fadd d0, d0, d3
+; CHECK-DAG: add [[TMP:w.*]], w0, w1
+; CHECK-DAG: add [[TMP]], [[TMP]], w2
+; CHECK-DAG: add w0, [[TMP]], w3
+; CHECK-O0-LABEL: test6
+; CHECK-O0: bl _gen6
+; CHECK-O0-DAG: fadd d0, d0, d1
+; CHECK-O0-DAG: fadd d0, d0, d2
+; CHECK-O0-DAG: fadd d0, d0, d3
+; CHECK-O0-DAG: add [[TMP:w.*]], w0, w1
+; CHECK-O0-DAG: add [[TMP]], [[TMP]], w2
+; CHECK-O0-DAG: add w0, [[TMP]], w3
+define swiftcc { double, i32 } @test6() {
+entry:
+ %call = call swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+ %v3 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 0
+ %v5 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 1
+ %v6 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 2
+ %v7 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 3
+ %v3.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 4
+ %v5.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 5
+ %v6.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 6
+ %v7.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 7
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+
+ %add.i = add nsw i32 %v3.i, %v5.i
+ %add1.i = add nsw i32 %add.i, %v6.i
+ %add2.i = add nsw i32 %add1.i, %v7.i
+
+ %Y = insertvalue { double, i32 } undef, double %add2, 0
+ %Z = insertvalue { double, i32 } %Y, i32 %add2.i, 1
+ ret { double, i32} %Z
+}
+
+declare swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+; CHECK-LABEL: _gen7
+; CHECK-DAG: mov w1, w0
+; CHECK-DAG: mov w2, w0
+; CHECK-DAG: mov w3, w0
+; CHECK: ret
+; CHECK-O0-LABEL: _gen7
+; CHECK-O0: str w0, [sp, #12]
+; CHECK-O0: ldr w1, [sp, #12]
+; CHECK-O0: ldr w2, [sp, #12]
+; CHECK-O0: ldr w3, [sp, #12]
+define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
+ %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0
+ %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1
+ %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2
+ %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3
+ ret { i32, i32, i32, i32 } %v3
+}
+
+; CHECK-LABEL: _gen9
+; CHECK: mov w1, w0
+; CHECK: mov w2, w0
+; CHECK: mov w3, w0
+; CHECK: ret
+; CHECK-O0-LABEL: _gen9
+; CHECK-O0: str w0, [sp, #12]
+; CHECK-O0: ldr w1, [sp, #12]
+; CHECK-O0: ldr w2, [sp, #12]
+; CHECK-O0: ldr w3, [sp, #12]
+define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
+ %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
+ %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1
+ %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2
+ %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3
+ ret { i8, i8, i8, i8 } %v3
+}
+
+; CHECK-LABEL: _gen10
+; CHECK: mov.16b v1, v0
+; CHECK: mov.16b v2, v0
+; CHECK: mov.16b v3, v0
+; CHECK: mov w1, w0
+; CHECK: mov w2, w0
+; CHECK: mov w3, w0
+; CHECK: ret
+define swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen10(double %keyd, i32 %keyi) {
+ %v0 = insertvalue { double, double, double, double, i32, i32, i32, i32 } undef, double %keyd, 0
+ %v1 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v0, double %keyd, 1
+ %v2 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v1, double %keyd, 2
+ %v3 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v2, double %keyd, 3
+ %v4 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v3, i32 %keyi, 4
+ %v5 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v4, i32 %keyi, 5
+ %v6 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v5, i32 %keyi, 6
+ %v7 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v6, i32 %keyi, 7
+ ret { double, double, double, double, i32, i32, i32, i32 } %v7
+}
+
+; CHECK-LABEL: _test11
+; CHECK: bl _gen11
+; CHECK: fadd.4s v0, v0, v1
+; CHECK: fadd.4s v0, v0, v2
+; CHECK: fadd.4s v0, v0, v3
+define swiftcc <4 x float> @test11() {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2
+ %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %add2 = fadd <4 x float> %add1, %v7
+ ret <4 x float> %add2
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+; CHECK-LABEL: _test12
+; CHECK: fadd.4s v0, v0, v1
+; CHECK: fadd.4s v0, v0, v2
+; CHECK: mov.16b v1, v3
+define swiftcc { <4 x float>, float } @test12() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2
+ %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0
+ %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1
+ ret { <4 x float>, float } %res
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=285417&r1=285416&r2=285417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Fri Oct 28 12:21:05 2016
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -disable-fp-elim < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck --check-prefix=CHECK-APPLE %s
+; RUN: llc -verify-machineinstrs -disable-fp-elim -enable-shrink-wrap=false < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck --check-prefix=CHECK-APPLE %s
; RUN: llc -verify-machineinstrs -disable-fp-elim -O0 < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck --check-prefix=CHECK-O0 %s
declare i8* @malloc(i64)
@@ -45,7 +45,7 @@ define float @caller(i8* %error_ref) {
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-APPLE: mov x0, x19
-; CHECK_APPLE: bl {{.*}}free
+; CHECK-APPLE: bl {{.*}}free
; CHECK-O0-LABEL: caller:
; CHECK-O0: mov x19
@@ -84,7 +84,7 @@ define float @caller2(i8* %error_ref) {
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-APPLE: mov x0, x19
-; CHECK_APPLE: bl {{.*}}free
+; CHECK-APPLE: bl {{.*}}free
; CHECK-O0-LABEL: caller2:
; CHECK-O0: mov x19
@@ -268,7 +268,7 @@ define float @caller3(i8* %error_ref) {
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-APPLE: mov x0, x19
-; CHECK_APPLE: bl {{.*}}free
+; CHECK-APPLE: bl {{.*}}free
; CHECK-O0-LABEL: caller3:
; spill x0
@@ -363,7 +363,7 @@ define float @caller4(i8* %error_ref) {
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-APPLE: mov x0, x19
-; CHECK_APPLE: bl {{.*}}free
+; CHECK-APPLE: bl {{.*}}free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
store %swift_error* null, %swift_error** %error_ptr_ref
@@ -405,3 +405,181 @@ entry:
%0 = tail call swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %error_ptr_ref)
ret float %0
}
+
+; CHECK-APPLE-LABEL: swifterror_clobber
+; CHECK-APPLE: mov [[REG:x[0-9]+]], x19
+; CHECK-APPLE: nop
+; CHECK-APPLE: mov x19, [[REG]]
+define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
+ call void asm sideeffect "nop", "~{x19}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: swifterror_reg_clobber
+; CHECK-APPLE: stp {{.*}}x19
+; CHECK-APPLE: nop
+; CHECK-APPLE: ldp {{.*}}x19
+define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
+ call void asm sideeffect "nop", "~{x19}"()
+ ret void
+}
+; CHECK-APPLE-LABEL: params_in_reg
+; Save callee saved registers and swifterror since it will be clobbered by the first call to params_in_reg2.
+; CHECK-APPLE: stp x19, x28, [sp
+; CHECK-APPLE: stp x27, x26, [sp
+; CHECK-APPLE: stp x25, x24, [sp
+; CHECK-APPLE: stp x23, x22, [sp
+; CHECK-APPLE: stp x21, x20, [sp
+; CHECK-APPLE: stp x29, x30, [sp
+; CHECK-APPLE: str x20, [sp
+; Store argument registers.
+; CHECK-APPLE: mov x23, x7
+; CHECK-APPLE: mov x24, x6
+; CHECK-APPLE: mov x25, x5
+; CHECK-APPLE: mov x26, x4
+; CHECK-APPLE: mov x27, x3
+; CHECK-APPLE: mov x28, x2
+; CHECK-APPLE: mov x21, x1
+; CHECK-APPLE: mov x22, x0
+; Setup call.
+; CHECK-APPLE: orr w0, wzr, #0x1
+; CHECK-APPLE: orr w1, wzr, #0x2
+; CHECK-APPLE: orr w2, wzr, #0x3
+; CHECK-APPLE: orr w3, wzr, #0x4
+; CHECK-APPLE: mov w4, #5
+; CHECK-APPLE: orr w5, wzr, #0x6
+; CHECK-APPLE: orr w6, wzr, #0x7
+; CHECK-APPLE: orr w7, wzr, #0x8
+; CHECK-APPLE: mov x20, xzr
+; CHECK-APPLE: mov x19, xzr
+; CHECK-APPLE: bl _params_in_reg2
+; Restore original arguments for next call.
+; CHECK-APPLE: mov x0, x22
+; CHECK-APPLE: mov x1, x21
+; CHECK-APPLE: mov x2, x28
+; CHECK-APPLE: mov x3, x27
+; CHECK-APPLE: mov x4, x26
+; CHECK-APPLE: mov x5, x25
+; CHECK-APPLE: mov x6, x24
+; CHECK-APPLE: mov x7, x23
+; Restore original swiftself argument and swifterror %err.
+; CHECK-APPLE: ldp x20, x19, [sp
+; CHECK-APPLE: bl _params_in_reg2
+; Restore calle save registers but don't clober swifterror x19.
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldp x29, x30, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldp x21, x20, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldp x23, x22, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldp x25, x24, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldp x27, x26, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ldr x28, [sp
+; CHECK-APPLE-NOT: x19
+; CHECK-APPLE: ret
+define swiftcc void @params_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ call swiftcc void @params_in_reg2(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i8* swiftself %8, %swift_error** nocapture swifterror %err)
+ ret void
+}
+declare swiftcc void @params_in_reg2(i64, i64, i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err)
+
+; CHECK-APPLE-LABEL: params_and_return_in_reg
+; Store callee saved registers.
+; CHECK-APPLE: stp x20, x28, [sp, #24
+; CHECK-APPLE: stp x27, x26, [sp
+; CHECK-APPLE: stp x25, x24, [sp
+; CHECK-APPLE: stp x23, x22, [sp
+; CHECK-APPLE: stp x21, x20, [sp
+; CHECK-APPLE: stp x29, x30, [sp
+; Save original arguments.
+; CHECK-APPLE: mov x23, x19
+; CHECK-APPLE: str x7, [sp, #16]
+; CHECK-APPLE: mov x24, x6
+; CHECK-APPLE: mov x25, x5
+; CHECK-APPLE: mov x26, x4
+; CHECK-APPLE: mov x27, x3
+; CHECK-APPLE: mov x28, x2
+; CHECK-APPLE: mov x21, x1
+; CHECK-APPLE: mov x22, x0
+; Setup call arguments.
+; CHECK-APPLE: orr w0, wzr, #0x1
+; CHECK-APPLE: orr w1, wzr, #0x2
+; CHECK-APPLE: orr w2, wzr, #0x3
+; CHECK-APPLE: orr w3, wzr, #0x4
+; CHECK-APPLE: mov w4, #5
+; CHECK-APPLE: orr w5, wzr, #0x6
+; CHECK-APPLE: orr w6, wzr, #0x7
+; CHECK-APPLE: orr w7, wzr, #0x8
+; CHECK-APPLE: mov x20, xzr
+; CHECK-APPLE: mov x19, xzr
+; CHECK-APPLE: bl _params_in_reg2
+; Store swifterror %error_ptr_ref.
+; CHECK-APPLE: str x19, [sp, #8]
+; Setup call arguments from original arguments.
+; CHECK-APPLE: mov x0, x22
+; CHECK-APPLE: mov x1, x21
+; CHECK-APPLE: mov x2, x28
+; CHECK-APPLE: mov x3, x27
+; CHECK-APPLE: mov x4, x26
+; CHECK-APPLE: mov x5, x25
+; CHECK-APPLE: mov x6, x24
+; CHECK-APPLE: ldp x7, x20, [sp, #16]
+; CHECK-APPLE: mov x19, x23
+; CHECK-APPLE: bl _params_and_return_in_reg2
+; Store return values.
+; CHECK-APPLE: mov x21, x0
+; CHECK-APPLE: mov x22, x1
+; CHECK-APPLE: mov x24, x2
+; CHECK-APPLE: mov x25, x3
+; CHECK-APPLE: mov x26, x4
+; CHECK-APPLE: mov x27, x5
+; CHECK-APPLE: mov x28, x6
+; CHECK-APPLE: mov x23, x7
+; Save swifterror %err.
+; CHECK-APPLE: str x19, [sp, #24]
+; Setup call.
+; CHECK-APPLE: orr w0, wzr, #0x1
+; CHECK-APPLE: orr w1, wzr, #0x2
+; CHECK-APPLE: orr w2, wzr, #0x3
+; CHECK-APPLE: orr w3, wzr, #0x4
+; CHECK-APPLE: mov w4, #5
+; CHECK-APPLE: orr w5, wzr, #0x6
+; CHECK-APPLE: orr w6, wzr, #0x7
+; CHECK-APPLE: orr w7, wzr, #0x8
+; CHECK-APPLE: mov x20, xzr
+; ... setup call with swiferror %error_ptr_ref.
+; CHECK-APPLE: ldr x19, [sp, #8]
+; CHECK-APPLE: bl _params_in_reg2
+; Restore return values for return from this function.
+; CHECK-APPLE: mov x0, x21
+; CHECK-APPLE: mov x1, x22
+; CHECK-APPLE: mov x2, x24
+; CHECK-APPLE: mov x3, x25
+; CHECK-APPLE: mov x4, x26
+; CHECK-APPLE: mov x5, x27
+; CHECK-APPLE: mov x6, x28
+; CHECK-APPLE: mov x7, x23
+; Restore swifterror %err and callee save registers.
+; CHECK-APPLE: ldp x19, x28, [sp, #24
+; CHECK-APPLE: ldp x29, x30, [sp
+; CHECK-APPLE: ldp x21, x20, [sp
+; CHECK-APPLE: ldp x23, x22, [sp
+; CHECK-APPLE: ldp x25, x24, [sp
+; CHECK-APPLE: ldp x27, x26, [sp
+; CHECK-APPLE: ret
+define swiftcc { i64, i64, i64, i64, i64, i64, i64, i64 } @params_and_return_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ %val = call swiftcc { i64, i64, i64, i64, i64, i64, i64, i64 } @params_and_return_in_reg2(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i8* swiftself %8, %swift_error** nocapture swifterror %err)
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ ret { i64, i64, i64, i64, i64, i64, i64, i64 } %val
+}
+
+declare swiftcc { i64, i64, i64, i64, i64, i64, i64, i64 } @params_and_return_in_reg2(i64, i64, i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err)
Modified: llvm/trunk/test/CodeGen/ARM/swift-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swift-return.ll?rev=285417&r1=285416&r2=285417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/swift-return.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/swift-return.ll Fri Oct 28 12:21:05 2016
@@ -131,3 +131,184 @@ entry:
}
declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
+
+; The return value {float, float, float, float} will be returned via registers
+; s0-s3.
+; CHECK-LABEL: test4:
+; CHECK: bl _gen4
+; CHECK: vadd.f32 s0, s0, s1
+; CHECK: vadd.f32 s0, s0, s2
+; CHECK: vadd.f32 s0, s0, s3
+; CHECK-O0-LABEL: test4:
+; CHECK-O0: bl _gen4
+; CHECK-O0: vadd.f32 s0, s0, s1
+; CHECK-O0: vadd.f32 s0, s0, s2
+; CHECK-O0: vadd.f32 s0, s0, s3
+define float @test4(float %key) #0 {
+entry:
+ %key.addr = alloca float, align 4
+ store float %key, float* %key.addr, align 4
+ %0 = load float, float* %key.addr, align 4
+ %call = call swiftcc { float, float, float, float } @gen4(float %0)
+
+ %v3 = extractvalue { float, float, float, float } %call, 0
+ %v5 = extractvalue { float, float, float, float } %call, 1
+ %v6 = extractvalue { float, float, float, float } %call, 2
+ %v7 = extractvalue { float, float, float, float } %call, 3
+
+ %add = fadd float %v3, %v5
+ %add1 = fadd float %add, %v6
+ %add2 = fadd float %add1, %v7
+ ret float %add2
+}
+
+declare swiftcc { float, float, float, float } @gen4(float %key)
+
+; CHECK-LABEL: test5
+; CHECK: bl _gen5
+; CHECK: vadd.f64 [[TMP:d.*]], d0, d1
+; CHECK: vadd.f64 [[TMP]], [[TMP]], d2
+; CHECK: vadd.f64 d0, [[TMP]], d3
+define swiftcc double @test5() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double } @gen5()
+
+ %v3 = extractvalue { double, double, double, double } %call, 0
+ %v5 = extractvalue { double, double, double, double } %call, 1
+ %v6 = extractvalue { double, double, double, double } %call, 2
+ %v7 = extractvalue { double, double, double, double } %call, 3
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+ ret double %add2
+}
+
+declare swiftcc { double, double, double, double } @gen5()
+
+
+; CHECK-LABEL: test6
+; CHECK: bl _gen6
+; CHECK-DAG: vadd.f64 [[TMP:d.*]], d0, d1
+; CHECK-DAG: add r0, r0, r1
+; CHECK-DAG: add r0, r0, r2
+; CHECK-DAG: add r0, r0, r3
+; CHECK-DAG: vadd.f64 [[TMP]], [[TMP]], d2
+; CHECK-DAG: vadd.f64 d0, [[TMP]], d3
+define swiftcc { double, i32 } @test6() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+ %v3 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 0
+ %v5 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 1
+ %v6 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 2
+ %v7 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 3
+ %v3.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 4
+ %v5.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 5
+ %v6.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 6
+ %v7.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 7
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+
+ %add.i = add nsw i32 %v3.i, %v5.i
+ %add1.i = add nsw i32 %add.i, %v6.i
+ %add2.i = add nsw i32 %add1.i, %v7.i
+
+ %Y = insertvalue { double, i32 } undef, double %add2, 0
+ %Z = insertvalue { double, i32 } %Y, i32 %add2.i, 1
+ ret { double, i32} %Z
+}
+
+declare swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+; CHECK-LABEL: gen7
+; CHECK: mov r1, r0
+; CHECK: mov r2, r0
+; CHECK: mov r3, r0
+; CHECK: bx lr
+define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
+ %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0
+ %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1
+ %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2
+ %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3
+ ret { i32, i32, i32, i32 } %v3
+}
+
+; CHECK-LABEL: gen9
+; CHECK: mov r1, r0
+; CHECK: mov r2, r0
+; CHECK: mov r3, r0
+; CHECK: bx lr
+define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
+ %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
+ %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1
+ %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2
+ %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3
+ ret { i8, i8, i8, i8 } %v3
+}
+; CHECK-LABEL: gen10
+; CHECK-DAG: vmov.f64 d1, d0
+; CHECK-DAG: mov r1, r0
+; CHECK-DAG: mov r2, r0
+; CHECK-DAG: mov r3, r0
+; CHECK-DAG: vmov.f64 d2, d0
+; CHECK-DAG: vmov.f64 d3, d0
+; CHECK-DAG: bx lr
+define swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen10(double %keyd, i32 %keyi) {
+ %v0 = insertvalue { double, double, double, double, i32, i32, i32, i32 } undef, double %keyd, 0
+ %v1 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v0, double %keyd, 1
+ %v2 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v1, double %keyd, 2
+ %v3 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v2, double %keyd, 3
+ %v4 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v3, i32 %keyi, 4
+ %v5 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v4, i32 %keyi, 5
+ %v6 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v5, i32 %keyi, 6
+ %v7 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v6, i32 %keyi, 7
+ ret { double, double, double, double, i32, i32, i32, i32 } %v7
+}
+
+
+; CHECK-LABEL: test11
+; CHECK: bl _gen11
+; CHECK: vadd.f32 [[TMP:q.*]], q0, q1
+; CHECK: vadd.f32 [[TMP]], [[TMP]], q2
+; CHECK: vadd.f32 q0, [[TMP]], q3
+define swiftcc <4 x float> @test11() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2
+ %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %add2 = fadd <4 x float> %add1, %v7
+ ret <4 x float> %add2
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+; CHECK-LABEL: test12
+; CHECK-DAG: vadd.f32 [[TMP:q.*]], q0, q1
+; CHECK-DAG: vmov.f32 s4, s12
+; CHECK-DAG: vadd.f32 q0, [[TMP]], q2
+define swiftcc { <4 x float>, float } @test12() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2
+ %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0
+ %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1
+ ret { <4 x float>, float } %res
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
Modified: llvm/trunk/test/CodeGen/ARM/swifterror.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=285417&r1=285416&r2=285417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/swifterror.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/swifterror.ll Fri Oct 28 12:21:05 2016
@@ -394,3 +394,124 @@ entry:
%0 = tail call swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %error_ptr_ref)
ret float %0
}
+
+; CHECK-APPLE-LABEL: swifterror_clobber
+; CHECK-APPLE: mov [[REG:r[0-9]+]], r6
+; CHECK-APPLE: nop
+; CHECK-APPLE: mov r6, [[REG]]
+define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
+ call void asm sideeffect "nop", "~{r6}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: swifterror_reg_clobber
+; CHECK-APPLE: push {{.*}}r6
+; CHECK-APPLE: nop
+; CHECK-APPLE: pop {{.*}}r6
+define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
+ call void asm sideeffect "nop", "~{r6}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: _params_in_reg
+; Store callee saved registers excluding swifterror.
+; CHECK-APPLE: push {r8, r10, r11, r4, r5, r7, lr}
+; Store swiftself (r10) and swifterror (r6).
+; CHECK-APPLE: str r6, [sp, #4]
+; CHECK-APPLE: str r10, [sp]
+; Store arguments.
+; CHECK-APPLE: mov r4, r3
+; CHECK-APPLE: mov r5, r2
+; CHECK-APPLE: mov r8, r1
+; CHECK-APPLE: mov r11, r0
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: mov r6, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Restore original arguments.
+; CHECK-APPLE: ldr r10, [sp]
+; CHECK-APPLE: ldr r6, [sp, #4]
+; CHECK-APPLE: mov r0, r11
+; CHECK-APPLE: mov r1, r8
+; CHECK-APPLE: mov r2, r5
+; CHECK-APPLE: mov r3, r4
+; CHECK-APPLE: bl _params_in_reg2
+; CHECK-APPLE: sub sp, r7, #20
+; CHECK-APPLE: pop {r8, r10, r11, r4, r5, r7, pc}
+define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ call swiftcc void @params_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
+ ret void
+}
+declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
+
+; CHECK-LABEL: params_and_return_in_reg
+; CHECK-APPLE: push {r8, r10, r11, r4, r5, r7, lr}
+; Store swifterror and swiftself
+; CHECK-APPLE: mov r4, r6
+; CHECK-APPLE: str r10, [sp, #12]
+; Store arguments.
+; CHECK-APPLE: str r3, [sp, #8]
+; CHECK-APPLE: mov r5, r2
+; CHECK-APPLE: mov r8, r1
+; CHECK-APPLE: mov r11, r0
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: mov r6, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Restore original arguments.
+; CHECK-APPLE: ldr r3, [sp, #8]
+; CHECK-APPLE: ldr r10, [sp, #12]
+; Store %error_ptr_ref;
+; CHECK-APPLE: str r6, [sp, #4]
+; Restore original arguments.
+; CHECK-APPLE: mov r0, r11
+; CHECK-APPLE: mov r1, r8
+; CHECK-APPLE: mov r2, r5
+; CHECK-APPLE: mov r6, r4
+; CHECK-APPLE: bl _params_and_return_in_reg2
+; Store swifterror return %err;
+; CHECK-APPLE: str r6, [sp, #12]
+; Load swifterror value %error_ptr_ref.
+; CHECK-APPLE: ldr r6, [sp, #4]
+; Save return values.
+; CHECK-APPLE: mov r5, r0
+; CHECK-APPLE: mov r4, r1
+; CHECK-APPLE: mov r8, r2
+; CHECK-APPLE: mov r11, r3
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Load swifterror %err;
+; CHECK-APPLE: ldr r6, [sp, #12]
+; Restore return values for returning.
+; CHECK-APPLE: mov r0, r5
+; CHECK-APPLE: mov r1, r4
+; CHECK-APPLE: mov r2, r8
+; CHECK-APPLE: mov r3, r11
+; CHECK-APPLE: sub sp, r7, #20
+; CHECK-APPLE: pop {r8, r10, r11, r4, r5, r7, pc}
+define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ %val = call swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ ret { i32, i32, i32, i32 }%val
+}
+
+declare swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
Modified: llvm/trunk/test/CodeGen/X86/swift-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/swift-return.ll?rev=285417&r1=285416&r2=285417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/swift-return.ll (original)
+++ llvm/trunk/test/CodeGen/X86/swift-return.ll Fri Oct 28 12:21:05 2016
@@ -204,3 +204,170 @@ define swiftcc void @foo(i64* sret %agg.
store i64 %val, i64* %agg.result
ret void
}
+
+; CHECK-LABEL: test5
+; CHECK: callq gen5
+; CHECK: addsd %xmm1, %xmm0
+; CHECK: addsd %xmm2, %xmm0
+; CHECK: addsd %xmm3, %xmm0
+define swiftcc double @test5() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double } @gen5()
+
+ %v3 = extractvalue { double, double, double, double } %call, 0
+ %v5 = extractvalue { double, double, double, double } %call, 1
+ %v6 = extractvalue { double, double, double, double } %call, 2
+ %v7 = extractvalue { double, double, double, double } %call, 3
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+ ret double %add2
+}
+
+declare swiftcc { double, double, double, double } @gen5()
+
+
+; CHECK-LABEL: test6
+; CHECK: callq gen6
+; CHECK: addsd %xmm1, %xmm0
+; CHECK: addsd %xmm2, %xmm0
+; CHECK: addsd %xmm3, %xmm0
+; CHECK: addq %rdx, %rax
+; CHECK: addq %rcx, %rax
+; CHECK: addq %r8, %rax
+define swiftcc { double, i64 } @test6() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen6()
+
+ %v3 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 0
+ %v5 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 1
+ %v6 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 2
+ %v7 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 3
+ %v3.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 4
+ %v5.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 5
+ %v6.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 6
+ %v7.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 7
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+
+ %add.i = add nsw i64 %v3.i, %v5.i
+ %add1.i = add nsw i64 %add.i, %v6.i
+ %add2.i = add nsw i64 %add1.i, %v7.i
+
+ %Y = insertvalue { double, i64 } undef, double %add2, 0
+ %Z = insertvalue { double, i64 } %Y, i64 %add2.i, 1
+ ret { double, i64} %Z
+}
+
+declare swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen6()
+
+; CHECK-LABEL: gen7
+; CHECK: movl %edi, %eax
+; CHECK: movl %edi, %edx
+; CHECK: movl %edi, %ecx
+; CHECK: movl %edi, %r8d
+; CHECK: retq
+define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
+ %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0
+ %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1
+ %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2
+ %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3
+ ret { i32, i32, i32, i32 } %v3
+}
+
+; CHECK-LABEL: gen8
+; CHECK: movq %rdi, %rax
+; CHECK: movq %rdi, %rdx
+; CHECK: movq %rdi, %rcx
+; CHECK: movq %rdi, %r8
+; CHECK: retq
+define swiftcc { i64, i64, i64, i64 } @gen8(i64 %key) {
+ %v0 = insertvalue { i64, i64, i64, i64 } undef, i64 %key, 0
+ %v1 = insertvalue { i64, i64, i64, i64 } %v0, i64 %key, 1
+ %v2 = insertvalue { i64, i64, i64, i64 } %v1, i64 %key, 2
+ %v3 = insertvalue { i64, i64, i64, i64 } %v2, i64 %key, 3
+ ret { i64, i64, i64, i64 } %v3
+}
+
+; CHECK-LABEL: gen9
+; CHECK: movl %edi, %eax
+; CHECK: movl %edi, %edx
+; CHECK: movl %edi, %ecx
+; CHECK: movl %edi, %r8d
+; CHECK: retq
+define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
+ %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
+ %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1
+ %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2
+ %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3
+ ret { i8, i8, i8, i8 } %v3
+}
+; CHECK-LABEL: gen10
+; CHECK: movaps %xmm0, %xmm1
+; CHECK: movaps %xmm0, %xmm2
+; CHECK: movaps %xmm0, %xmm3
+; CHECK: movq %rdi, %rax
+; CHECK: movq %rdi, %rdx
+; CHECK: movq %rdi, %rcx
+; CHECK: movq %rdi, %r8
+; CHECK: retq
+define swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen10(double %keyd, i64 %keyi) {
+ %v0 = insertvalue { double, double, double, double, i64, i64, i64, i64 } undef, double %keyd, 0
+ %v1 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v0, double %keyd, 1
+ %v2 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v1, double %keyd, 2
+ %v3 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v2, double %keyd, 3
+ %v4 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v3, i64 %keyi, 4
+ %v5 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v4, i64 %keyi, 5
+ %v6 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v5, i64 %keyi, 6
+ %v7 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v6, i64 %keyi, 7
+ ret { double, double, double, double, i64, i64, i64, i64 } %v7
+}
+
+
+; CHECK-LABEL: test11
+; CHECK: callq gen11
+; CHECK: addps %xmm1, %xmm0
+; CHECK: addps %xmm2, %xmm0
+; CHECK: addps %xmm3, %xmm0
+define swiftcc <4 x float> @test11() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2
+ %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %add2 = fadd <4 x float> %add1, %v7
+ ret <4 x float> %add2
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+; CHECK-LABEL: test12
+; CHECK: callq gen12
+; CHECK: addps %xmm1, %xmm0
+; CHECK: addps %xmm2, %xmm0
+; CHECK: movaps %xmm3, %xmm1
+define swiftcc { <4 x float>, float } @test12() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2
+ %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0
+ %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1
+ ret { <4 x float>, float } %res
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
Modified: llvm/trunk/test/CodeGen/X86/swifterror.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/swifterror.ll?rev=285417&r1=285416&r2=285417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/swifterror.ll (original)
+++ llvm/trunk/test/CodeGen/X86/swifterror.ll Fri Oct 28 12:21:05 2016
@@ -519,3 +519,154 @@ cont:
tail call swiftcc void undef(%swift_error** nocapture swifterror %0)
ret void
}
+
+; CHECK-APPLE-LABEL: swifterror_clobber
+; CHECK-APPLE: movq %r12, [[REG:%.*]]
+; CHECK-APPLE: nop
+; CHECK-APPLE: movq [[REG]], %r12
+define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
+ call void asm sideeffect "nop", "~{r12}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: swifterror_reg_clobber
+; CHECK-APPLE: pushq %r12
+; CHECK-APPLE: nop
+; CHECK-APPLE: popq %r12
+define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
+ call void asm sideeffect "nop", "~{r12}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: params_in_reg
+; Save callee save registers to store clobbered arugments.
+; CHECK-APPLE: pushq %rbp
+; CHECK-APPLE: pushq %r15
+; CHECK-APPLE: pushq %r14
+; Clobbered swiftself register.
+; CHECK-APPLE: pushq %r13
+; CHECK-APPLE: pushq %rbx
+; CHECK-APPLE: subq $48, %rsp
+; Save arguments.
+; CHECK-APPLE: movq %r12, 32(%rsp)
+; CHECK-APPLE: movq %r13, 24(%rsp)
+; CHECK-APPLE: movq %r9, 16(%rsp)
+; CHECK-APPLE: movq %r8, 8(%rsp)
+; CHECK-APPLE: movq %rcx, %r14
+; CHECK-APPLE: movq %rdx, %r15
+; CHECK-APPLE: movq %rsi, %rbx
+; CHECK-APPLE: movq %rdi, %rbp
+; Setup call.
+; CHECK-APPLE: movl $1, %edi
+; CHECK-APPLE: movl $2, %esi
+; CHECK-APPLE: movl $3, %edx
+; CHECK-APPLE: movl $4, %ecx
+; CHECK-APPLE: movl $5, %r8d
+; CHECK-APPLE: movl $6, %r9d
+; CHECK-APPLE: xorl %r13d, %r13d
+; CHECK-APPLE: xorl %r12d, %r12d
+; CHECK-APPLE: callq _params_in_reg2
+; Setup second call with stored arguments.
+; CHECK-APPLE: movq %rbp, %rdi
+; CHECK-APPLE: movq %rbx, %rsi
+; CHECK-APPLE: movq %r15, %rdx
+; CHECK-APPLE: movq %r14, %rcx
+; CHECK-APPLE: movq 8(%rsp), %r8
+; CHECK-APPLE: movq 16(%rsp), %r9
+; CHECK-APPLE: movq 24(%rsp), %r13
+; CHECK-APPLE: movq 32(%rsp), %r12
+; CHECK-APPLE: callq _params_in_reg2
+; CHECK-APPLE: addq $48, %rsp
+; CHECK-APPLE: popq %rbx
+; CHECK-APPLE: popq %r13
+; CHECK-APPLE: popq %r14
+; CHECK-APPLE: popq %r15
+; CHECK-APPLE: popq %rbp
+define swiftcc void @params_in_reg(i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ call swiftcc void @params_in_reg2(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i8* swiftself %6, %swift_error** nocapture swifterror %err)
+ ret void
+}
+declare swiftcc void @params_in_reg2(i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err)
+
+; CHECK-APPLE-LABEL: params_and_return_in_reg
+; CHECK-APPLE: pushq %rbp
+; CHECK-APPLE: pushq %r15
+; CHECK-APPLE: pushq %r14
+; CHECK-APPLE: pushq %r13
+; CHECK-APPLE: pushq %rbx
+; CHECK-APPLE: subq $48, %rsp
+; Store arguments.
+; CHECK-APPLE: movq %r12, %r14
+; CHECK-APPLE: movq %r13, (%rsp)
+; CHECK-APPLE: movq %r9, 32(%rsp)
+; CHECK-APPLE: movq %r8, 24(%rsp)
+; CHECK-APPLE: movq %rcx, 16(%rsp)
+; CHECK-APPLE: movq %rdx, %r15
+; CHECK-APPLE: movq %rsi, %rbx
+; CHECK-APPLE: movq %rdi, %rbp
+; Setup call that clobbers all argument registers.
+; CHECK-APPLE: movl $1, %edi
+; CHECK-APPLE: movl $2, %esi
+; CHECK-APPLE: movl $3, %edx
+; CHECK-APPLE: movl $4, %ecx
+; CHECK-APPLE: movl $5, %r8d
+; CHECK-APPLE: movl $6, %r9d
+; CHECK-APPLE: xorl %r13d, %r13d
+; CHECK-APPLE: xorl %r12d, %r12d
+; CHECK-APPLE: callq _params_in_reg2
+; Store error_ptr_ref for later use.
+; CHECK-APPLE: movq %r12, 8(%rsp)
+; Restore original arguments.
+; CHECK-APPLE: movq %rbp, %rdi
+; CHECK-APPLE: movq %rbx, %rsi
+; CHECK-APPLE: movq %r15, %rdx
+; CHECK-APPLE: movq 16(%rsp), %rcx
+; CHECK-APPLE: movq 24(%rsp), %r8
+; CHECK-APPLE: movq 32(%rsp), %r9
+; CHECK-APPLE: movq (%rsp), %r13
+; CHECK-APPLE: movq %r14, %r12
+; CHECK-APPLE: callq _params_and_return_in_reg2
+; Store return values in callee saved registers.
+; CHECK-APPLE: movq %rax, %rbx
+; CHECK-APPLE: movq %rdx, %rbp
+; CHECK-APPLE: movq %rcx, %r15
+; CHECK-APPLE: movq %r8, %r14
+; Store the swifterror return value (%err).
+; CHECK-APPLE: movq %r12, (%rsp)
+; Setup call.
+; CHECK-APPLE: movl $1, %edi
+; CHECK-APPLE: movl $2, %esi
+; CHECK-APPLE: movl $3, %edx
+; CHECK-APPLE: movl $4, %ecx
+; CHECK-APPLE: movl $5, %r8d
+; CHECK-APPLE: movl $6, %r9d
+; CHECK-APPLE: xorl %r13d, %r13d
+; Restore the swifterror value of error_ptr_ref.
+; CHECK-APPLE: movq 8(%rsp), %r12
+; CHECK-APPLE: callq _params_in_reg2
+; Restore the return values of _params_and_return_in_reg2.
+; CHECK-APPLE: movq %rbx, %rax
+; CHECK-APPLE: movq %rbp, %rdx
+; CHECK-APPLE: movq %r15, %rcx
+; CHECK-APPLE: movq %r14, %r8
+; Restore the swiferror value of err.
+; CHECK-APPLE: movq (%rsp), %r12
+; CHECK-APPLE: addq $48, %rsp
+; CHECK-APPLE: popq %rbx
+; CHECK-APPLE: popq %r13
+; CHECK-APPLE: popq %r14
+; CHECK-APPLE: popq %r15
+; CHECK-APPLE: popq %rbp
+define swiftcc { i64, i64, i64, i64} @params_and_return_in_reg(i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ %val = call swiftcc { i64, i64, i64, i64 } @params_and_return_in_reg2(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i8* swiftself %6, %swift_error** nocapture swifterror %err)
+ call swiftcc void @params_in_reg2(i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ ret { i64, i64, i64, i64 }%val
+}
+
+declare swiftcc { i64, i64, i64, i64 } @params_and_return_in_reg2(i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err)
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