[PATCH] D26011: [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64

[Igor Breger via llvm-commits]

igorb accepted this revision.
igorb added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:19858
+  // AVX512DQ - extend to 512 bit vector.
+  if (Subtarget.hasDQI()) {
+    assert(!Subtarget.hasVLX() && "AVX512DQVL vXi64 multiply is legal");
----------------
Hello,
It is possible to implement this logic in td file,  similar to  multiclass avx512_var_shift_w_lowering<..> implementation.


Repository:
  rL LLVM

https://reviews.llvm.org/D26011