[PATCH] D25577: AMDGPU/SI: Handle hazard with > 8 byte VMEM stores

[Matt Arsenault via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with minor cleanups



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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:373
+  unsigned Opcode = MI.getOpcode();
+  const MCInstrDesc &Desc = TII->get(Opcode);
+
----------------
MI.getDesc


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:375-376
+
+  if (!MI.mayStore())
+    return -1;
+
----------------
Move to the beginning?


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:386-387
+    // instruction is not using a register in the soffset field.
+    const MachineOperand *SOffset =
+    TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
+    // If we have no soffset operand, then assume this field has been
----------------
second line should be indented (although it looks like it might fit on one)


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:417-420
+  // This checks for the hazard where VMEM instructions that store more than
+  // 8 bytes can have there store data over written by the next instruction.
+  if (!ST.has12DWordStoreHazard())
+    return 0;
----------------
Move to beginning


https://reviews.llvm.org/D25577