[PATCH] D18049: AMDGPU/SI: Make i16 a legal type for VI subtargets

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/BUFInstructions.td:962-963
+
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
----------------
Originally I was avoiding these by promoting the load return type and truncating. Is this the same or is there an advantage from known bits types of things knowing it is really a 32-bit extload?


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:1916
         (SetCC->getConstantOperandVal(1) == 1 &&
+         isCFIntrinsic(Intr) &&
          cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
----------------
Why is this part of the patch? This looks unrelated


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:3428-3429
+  MVT NVT = MVT::i32;
+  unsigned ExtOp;
+  ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+
----------------
Define on same line


https://reviews.llvm.org/D18049