[PATCH] D18049: AMDGPU/SI: Make i16 a legal type for VI subtargets

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 26 09:44:20 PDT 2016

arsenm added inline comments.

Comment at: lib/Target/AMDGPU/BUFInstructions.td:962-963
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
+defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
Originally I was avoiding these by promoting the load return type and truncating. Is this the same or is there an advantage from known bits types of things knowing it is really a 32-bit extload?

Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:1916
         (SetCC->getConstantOperandVal(1) == 1 &&
+         isCFIntrinsic(Intr) &&
          cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
Why is this part of the patch? This looks unrelated

Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:3428-3429
+  MVT NVT = MVT::i32;
+  unsigned ExtOp;
Define on same line


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