[PATCH] D25975: AMDGPU/SI: Make f16 a legal type for VI subtargets

Tom Stellard via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 26 07:47:56 PDT 2016

tstellarAMD added inline comments.

Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:172-182
 def int_amdgcn_ldexp : Intrinsic<
-  [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
+  [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_anyint_ty], [IntrNoMem]
 def int_amdgcn_frexp_mant : Intrinsic<
   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
Can these changes be done in a different patch?  They change the intrinsic signature, and will require updating any users of this intrinsic in external projects.

Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:85-86
     addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
+    addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
+    addRegisterClass(MVT::f16, &AMDGPU::VGPR_32RegClass);
+  }
There is a 1-to-1 mapping between types and register classes, so you can drop the first addRegisterClass(MVT::f16, ... ) call


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