[PATCH] D25966: [AArch64] Lower multiplication by a constant int to shl+add+shl

[Haicheng Wu via llvm-commits]

haicheng created this revision.
haicheng added reviewers: mcrosier, Gerolf.
haicheng added a subscriber: llvm-commits.
haicheng set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

GCC can lower a = b * C where C = (2^n + 1) * 2^m to

  add     w0, w0, w0, lsl m
  lsl     w0, w0, n

also lower C = (2^n - 1) * 2^m to

  lsl     w1, w0, m
  sub     w0, w1, w0
  lsl     w0, w0, n

LLVM cannot do either above transformations and generate code like this

  mov     w8, C    
  mul     w0, w0, w8 

This change considers the first case, since the second case requires an extra instruction.  The change is also very conservative to try not to touch the mul that can be folded into s(u)mull, madd(sub), s(u)madd(sub)l since their costs seem unknown during ISelLowering.

I am also open to suggestions about a better place (machine-combiner???) to implement the transformation.  If I have the information of the cycles of 32 and 64bit mul, I can consider more constants such as C = (2^m + 1) * (2^n+1), C = (2^m + 1) * 2^n + 1, or C = ((2^m + 1) * 2^n + 1) * 2^p


Repository:
  rL LLVM

https://reviews.llvm.org/D25966

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-mul.ll
  test/CodeGen/AArch64/mul_pow2.ll

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