[llvm] r285046 - [InstCombine] auto-generate checks

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 24 17:44:02 PDT 2016


Author: spatel
Date: Mon Oct 24 19:44:02 2016
New Revision: 285046

URL: http://llvm.org/viewvc/llvm-project?rev=285046&view=rev
Log:
[InstCombine] auto-generate checks

Modified:
    llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll

Modified: llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll?rev=285046&r1=285045&r2=285046&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll Mon Oct 24 19:44:02 2016
@@ -1,82 +1,97 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
-; CHECK-LABEL: @t1
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: sext
+; This is the canonical form for a type-changing min/max.
 define i64 @t1(i32 %a) {
-  ; This is the canonical form for a type-changing min/max.
+; CHECK-LABEL: @t1(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, 5
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 5
+; CHECK-NEXT:    [[TMP3:%.*]] = sext i32 [[TMP2]] to i64
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
   %1 = icmp slt i32 %a, 5
   %2 = select i1 %1, i32 %a, i32 5
   %3 = sext i32 %2 to i64
   ret i64 %3
 }
 
-; CHECK-LABEL: @t2
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: sext
+; Check this is converted into canonical form, as above.
 define i64 @t2(i32 %a) {
-  ; Check this is converted into canonical form, as above.
+; CHECK-LABEL: @t2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, 5
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 5
+; CHECK-NEXT:    [[TMP3:%.*]] = sext i32 [[TMP2]] to i64
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
   %1 = icmp slt i32 %a, 5
   %2 = sext i32 %a to i64
   %3 = select i1 %1, i64 %2, i64 5
   ret i64 %3
 }
 
-; CHECK-LABEL: @t3
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: zext
+; Same as @t2, with flipped operands and zext instead of sext.
 define i64 @t3(i32 %a) {
-  ; Same as @t2, with flipped operands and zext instead of sext.
+; CHECK-LABEL: @t3(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 %a, 5
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 5
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
   %1 = icmp ult i32 %a, 5
   %2 = zext i32 %a to i64
   %3 = select i1 %1, i64 5, i64 %2
   ret i64 %3
 }
 
-; CHECK-LABEL: @t4
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: trunc
+; Same again, with trunc.
 define i32 @t4(i64 %a) {
-  ; Same again, with trunc.
+; CHECK-LABEL: @t4(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 %a, 5
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 %a, i64 5
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
   %1 = icmp slt i64 %a, 5
   %2 = trunc i64 %a to i32
   %3 = select i1 %1, i32 %2, i32 5
   ret i32 %3
 }
 
-; CHECK-LABEL: @t5
-; CHECK-NEXT: icmp
-; CHECK-NEXT: zext
-; CHECK-NEXT: select
+; Same as @t3, but with mismatched signedness between icmp and zext.
+; InstCombine should leave this alone.
 define i64 @t5(i32 %a) {
-  ; Same as @t3, but with mismatched signedness between icmp and zext.
-  ; InstCombine should leave this alone.
+; CHECK-LABEL: @t5(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, 5
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 %a to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i64 5, i64 [[TMP2]]
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
   %1 = icmp slt i32 %a, 5
   %2 = zext i32 %a to i64
   %3 = select i1 %1, i64 5, i64 %2
   ret i64 %3
 }
 
-; CHECK-LABEL: @t6
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: sitofp
 define float @t6(i32 %a) {
+; CHECK-LABEL: @t6(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, 0
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
+; CHECK-NEXT:    ret float [[TMP3]]
+;
   %1 = icmp slt i32 %a, 0
   %2 = select i1 %1, i32 %a, i32 0
   %3 = sitofp i32 %2 to float
   ret float %3
 }
 
-; CHECK-LABEL: @t7
-; CHECK-NEXT: icmp
-; CHECK-NEXT: select
-; CHECK-NEXT: trunc
 define i16 @t7(i32 %a) {
+; CHECK-LABEL: @t7(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, -32768
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 -32768
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
+; CHECK-NEXT:    ret i16 [[TMP3]]
+;
   %1 = icmp slt i32 %a, -32768
   %2 = trunc i32 %a to i16
   %3 = select i1 %1, i16 %2, i16 -32768
@@ -88,6 +103,16 @@ define i16 @t7(i32 %a) {
 ; which led to a canonicalization fight between different
 ; parts of instcombine.
 define i32 @t8(i64 %a, i32 %b) {
+; CHECK-LABEL: @t8(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 %a, -32767
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 %a, i64 -32767
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp slt i32 %b, 42
+; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i32 42, i32 [[TMP3]]
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], %b
+; CHECK-NEXT:    [[TMP7:%.*]] = zext i1 [[TMP6]] to i32
+; CHECK-NEXT:    ret i32 [[TMP7]]
+;
   %1 = icmp slt i64 %a, -32767
   %2 = select i1 %1, i64 %a, i64 -32767
   %3 = trunc i64 %2 to i32
@@ -99,14 +124,16 @@ define i32 @t8(i64 %a, i32 %b) {
 }
 
 ; Ensure this doesn't get converted to a min/max.
-; CHECK-LABEL: @t9
-; CHECK-NEXT: icmp
-; CHECK-NEXT: sext
-; CHECK-NEXT: 4294967295
-; CHECK-NEXT: ret
 define i64 @t9(i32 %a) {
+; CHECK-LABEL: @t9(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 %a, -1
+; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 %a to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i64 [[TMP2]], i64 4294967295
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
   %1 = icmp sgt i32 %a, -1
   %2 = sext i32 %a to i64
   %3 = select i1 %1, i64 %2, i64 4294967295
   ret i64 %3
 }
+




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