[llvm] r285029 - Use MachineInstr::mop_iterator instead of MIOperands; NFC
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 24 14:36:44 PDT 2016
Author: matze
Date: Mon Oct 24 16:36:43 2016
New Revision: 285029
URL: http://llvm.org/viewvc/llvm-project?rev=285029&view=rev
Log:
Use MachineInstr::mop_iterator instead of MIOperands; NFC
(Const)?MIOperands is equivalent to the C++ style
MachineInstr::mop_iterator. Use the latter for consistency except for a
few callers of MIOperands::analyzePhysReg().
Modified:
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Mon Oct 24 16:36:43 2016
@@ -1726,9 +1726,9 @@ static void computeLiveOuts(MachineFunct
const MachineInstr *MI = SU->getInstr();
if (MI->isPHI())
continue;
- for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
- if (MO->isReg() && MO->isUse()) {
- unsigned Reg = MO->getReg();
+ for (const MachineOperand &MO : MI->operands())
+ if (MO.isReg() && MO.isUse()) {
+ unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
Uses.insert(Reg);
else if (MRI.isAllocatable(Reg))
@@ -1737,9 +1737,9 @@ static void computeLiveOuts(MachineFunct
}
}
for (SUnit *SU : NS)
- for (ConstMIOperands MO(*SU->getInstr()); MO.isValid(); ++MO)
- if (MO->isReg() && MO->isDef() && !MO->isDead()) {
- unsigned Reg = MO->getReg();
+ for (const MachineOperand &MO : SU->getInstr()->operands())
+ if (MO.isReg() && MO.isDef() && !MO.isDead()) {
+ unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
if (!Uses.count(Reg))
LiveOutRegs.push_back(RegisterMaskPair(Reg, 0));
Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Mon Oct 24 16:36:43 2016
@@ -357,10 +357,10 @@ bool HexagonEarlyIfConversion::isValidCa
// update the use of it after predication). PHI uses will be updated
// to use a result of a MUX, and a MUX cannot be created for predicate
// registers.
- for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
- if (!MO->isReg() || !MO->isDef())
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg() || !MO.isDef())
continue;
- unsigned R = MO->getReg();
+ unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass)
@@ -375,10 +375,10 @@ bool HexagonEarlyIfConversion::isValidCa
bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const {
- for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) {
- if (!MO->isReg() || !MO->isUse())
+ for (const MachineOperand &MO : MI->operands()) {
+ if (!MO.isReg() || !MO.isUse())
continue;
- unsigned R = MO->getReg();
+ unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
const MachineInstr *DefI = MRI->getVRegDef(R);
@@ -454,10 +454,10 @@ unsigned HexagonEarlyIfConversion::count
const MachineBasicBlock *B) const {
unsigned PredDefs = 0;
for (auto &MI : *B) {
- for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
- if (!MO->isReg() || !MO->isDef())
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg() || !MO.isDef())
continue;
- unsigned R = MO->getReg();
+ unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) == &Hexagon::PredRegsRegClass)
@@ -669,14 +669,14 @@ void HexagonEarlyIfConversion::predicate
unsigned COpc = getCondStoreOpcode(Opc, IfTrue);
assert(COpc);
MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
- MIOperands MO(*MI);
+ MachineInstr::mop_iterator MOI = MI->operands_begin();
if (HII->isPostIncrement(*MI)) {
- MIB.addOperand(*MO);
- ++MO;
+ MIB.addOperand(*MOI);
+ ++MOI;
}
MIB.addReg(PredR);
- for (; MO.isValid(); ++MO)
- MIB.addOperand(*MO);
+ for (const MachineOperand &MO : make_range(MOI, MI->operands_end()))
+ MIB.addOperand(MO);
// Set memory references.
MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
@@ -949,9 +949,9 @@ void HexagonEarlyIfConversion::replacePh
MachineBasicBlock::iterator P, N = SB->getFirstNonPHI();
for (P = SB->begin(); P != N; ++P) {
MachineInstr &PN = *P;
- for (MIOperands MO(PN); MO.isValid(); ++MO)
- if (MO->isMBB() && MO->getMBB() == OldB)
- MO->setMBB(NewB);
+ for (MachineOperand &MO : PN.operands())
+ if (MO.isMBB() && MO.getMBB() == OldB)
+ MO.setMBB(NewB);
}
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Mon Oct 24 16:36:43 2016
@@ -1444,10 +1444,10 @@ bool HexagonGenInsert::removeDeadCode(Ma
bool AllDead = true;
SmallVector<unsigned,2> Regs;
- for (ConstMIOperands Op(*MI); Op.isValid(); ++Op) {
- if (!Op->isReg() || !Op->isDef())
+ for (const MachineOperand &MO : MI->operands()) {
+ if (!MO.isReg() || !MO.isDef())
continue;
- unsigned R = Op->getReg();
+ unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R) ||
!MRI->use_nodbg_empty(R)) {
AllDead = false;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp Mon Oct 24 16:36:43 2016
@@ -132,11 +132,11 @@ void HexagonGenMux::getDefsUses(const Ma
expandReg(*R++, Uses);
// Look over all operands, and collect explicit defs and uses.
- for (ConstMIOperands Mo(*MI); Mo.isValid(); ++Mo) {
- if (!Mo->isReg() || Mo->isImplicit())
+ for (const MachineOperand &MO : MI->operands()) {
+ if (!MO.isReg() || MO.isImplicit())
continue;
- unsigned R = Mo->getReg();
- BitVector &Set = Mo->isDef() ? Defs : Uses;
+ unsigned R = MO.getReg();
+ BitVector &Set = MO.isDef() ? Defs : Uses;
expandReg(R, Set);
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Mon Oct 24 16:36:43 2016
@@ -330,9 +330,9 @@ bool HexagonGenPredicate::isScalarPred(R
case Hexagon::C4_or_orn:
case Hexagon::C2_xor:
// Add operands to the queue.
- for (ConstMIOperands Mo(*DefI); Mo.isValid(); ++Mo)
- if (Mo->isReg() && Mo->isUse())
- WorkQ.push(Register(Mo->getReg()));
+ for (const MachineOperand &MO : DefI->operands())
+ if (MO.isReg() && MO.isUse())
+ WorkQ.push(Register(MO.getReg()));
break;
// All non-vector compares are ok, everything else is bad.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp?rev=285029&r1=285028&r2=285029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp Mon Oct 24 16:36:43 2016
@@ -96,9 +96,9 @@ void HexagonHazardRecognizer::EmitInstru
// Keep the set of definitions for each packet, which is used to determine
// if a .new can be used.
- for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
- if (MO->isReg() && MO->isDef() && !MO->isImplicit())
- RegDefs.insert(MO->getReg());
+ for (const MachineOperand &MO : MI->operands())
+ if (MO.isReg() && MO.isDef() && !MO.isImplicit())
+ RegDefs.insert(MO.getReg());
if (TII->isZeroCost(MI->getOpcode()))
return;
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