[PATCH] D25580: [PowerPC] Improve handling of BUILD_VECTOR nodes (integer results)
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 10:53:43 PDT 2016
echristo added inline comments.
Comment at: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp:225
const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isImm())
+ // PPC::ZERO and PPC::ZERO8 are register MachineOperand's but they really
+ // represent immediates.
> hfinkel wrote:
> > nemanjai wrote:
> > > echristo wrote:
> > > > This seems... weird.
> > > I agree. But the weirdness exists in the ISA as well. So I'm not sure how best to tackle this issue. Perhaps @hfinkel can provide a pointer regarding this.
> > This seems weird, in part, because it is not clear why it is necessary to handle this case in a special way. Is there a regression test that covers this? If we have a load with an absolute immediate address, but also a fixup, it is not clear why we'd ignore the fixup.
> I was hitting an assert from MachineOperand::getExpr() that the operand is not an expression (because it was register PPC::ZERO8). I'll investigate further what conditions lead to this, but it was in one of the projects/test-suite test cases (run with -mcpu=pwr9).
This definitely doesn't sound right. If you can narrow down a small assembly case that shows this we can handle it separately.
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