[llvm] r284627 - [InstSimplify] move one and add more tests for potential negation folds

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Oct 19 13:42:12 2016
New Revision: 284627

URL: http://llvm.org/viewvc/llvm-project?rev=284627&view=rev
Log:
[InstSimplify] move one and add more tests for potential negation folds

Added:
    llvm/trunk/test/Transforms/InstSimplify/negate.ll
Modified:
    llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll

Modified: llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll?rev=284627&r1=284626&r2=284627&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll Wed Oct 19 13:42:12 2016
@@ -29,15 +29,6 @@ define i64 @pow2b(i32 %x) {
   ret i64 %e2
 }
 
-define i32 @sub_neg_nuw(i32 %x, i32 %y) {
-; CHECK-LABEL: @sub_neg_nuw(
-; CHECK-NEXT:    ret i32 %x
-;
-  %neg = sub nuw i32 0, %y
-  %sub = sub i32 %x, %neg
-  ret i32 %sub
-}
-
 define i1 @and_of_icmps0(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps0(
 ; CHECK-NEXT:    ret i1 false

Added: llvm/trunk/test/Transforms/InstSimplify/negate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/negate.ll?rev=284627&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/negate.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/negate.ll Wed Oct 19 13:42:12 2016
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define i32 @negate_nuw(i32 %x) {
+; CHECK-LABEL: @negate_nuw(
+; CHECK-NEXT:    ret i32 0
+;
+  %neg = sub nuw i32 0, %x
+  ret i32 %neg
+}
+
+define <2 x i32> @negate_nuw_vec(<2 x i32> %x) {
+; CHECK-LABEL: @negate_nuw_vec(
+; CHECK-NEXT:    ret <2 x i32> zeroinitializer
+;
+  %neg = sub nuw <2 x i32> zeroinitializer, %x
+  ret <2 x i32> %neg
+}
+
+define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
+; CHECK-LABEL: @negate_zero_or_minsigned_nsw(
+; CHECK-NEXT:    [[SIGNBIT:%.*]] = and i8 %x, -128
+; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i8 0, [[SIGNBIT]]
+; CHECK-NEXT:    ret i8 [[NEG]]
+;
+  %signbit = and i8 %x, 128
+  %neg = sub nsw i8 0, %signbit
+  ret i8 %neg
+}
+
+define <2 x i8> @negate_zero_or_minsigned_nsw_vec(<2 x i8> %x) {
+; CHECK-LABEL: @negate_zero_or_minsigned_nsw_vec(
+; CHECK-NEXT:    [[SIGNBIT:%.*]] = shl <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT:    [[NEG:%.*]] = sub nsw <2 x i8> zeroinitializer, [[SIGNBIT]]
+; CHECK-NEXT:    ret <2 x i8> [[NEG]]
+;
+  %signbit = shl <2 x i8> %x, <i8 7, i8 7>
+  %neg = sub nsw <2 x i8> zeroinitializer, %signbit
+  ret <2 x i8> %neg
+}
+
+define i8 @negate_zero_or_minsigned(i8 %x) {
+; CHECK-LABEL: @negate_zero_or_minsigned(
+; CHECK-NEXT:    [[SIGNBIT:%.*]] = shl i8 %x, 7
+; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[SIGNBIT]]
+; CHECK-NEXT:    ret i8 [[NEG]]
+;
+  %signbit = shl i8 %x, 7
+  %neg = sub i8 0, %signbit
+  ret i8 %neg
+}
+
+define <2 x i8> @negate_zero_or_minsigned_vec(<2 x i8> %x) {
+; CHECK-LABEL: @negate_zero_or_minsigned_vec(
+; CHECK-NEXT:    [[SIGNBIT:%.*]] = and <2 x i8> %x, <i8 -128, i8 -128>
+; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[SIGNBIT]]
+; CHECK-NEXT:    ret <2 x i8> [[NEG]]
+;
+  %signbit = and <2 x i8> %x, <i8 128, i8 128>
+  %neg = sub <2 x i8> zeroinitializer, %signbit
+  ret <2 x i8> %neg
+}
+