[PATCH] D24808: [AArch64] Avoid materializing 0.0 when generating FP CSEL

[Sebastian Pop via llvm-commits]

sebpop added a comment.

In https://reviews.llvm.org/D24808#554492, @evandro wrote:

> In https://reviews.llvm.org/D24808#548901, @MatzeB wrote:
>
> > Wouldn't this work with any constant? Should we consider it for the common DAGCombiner?
>
>
> Thinking more about this suggestion, I think that this change improves code generation only if the comparison instruction has a form with an immediate operand encoding, which is very target dependent (e.g., AArch64).  Otherwise, if the target has to materialize the constant for the comparison, it can be used again by the selection (e.g., x86).


LGTM.  I think the patch looks good as it is.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4058
       // Transform "a == C ? C : x" to "a == C ? a : x" and "a != C ? x : C" to
       // "a != C ? x : a" to avoid materializing C.
       if (CTVal && CTVal == RHSVal && AArch64CC == AArch64CC::EQ)
----------------
The change from Evandro looks identical to this transform.
I don't see why we would need to do what Evandro proposes in the DAGcombine when this one is doing it at lowering.


Repository:
  rL LLVM

https://reviews.llvm.org/D24808