[PATCH] D25670: [ARM] Assign cost of scaling for Cortex-R52

[Javed Absar via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284460: [ARM] Assign cost of scaling for Cortex-R52 (authored by javed.absar).

Changed prior to commit:
  https://reviews.llvm.org/D25670?vs=74850&id=74958#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25670

Files:
  llvm/trunk/lib/Target/ARM/ARM.td
  llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll


Index: llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -1,8 +1,9 @@
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 ; Should use scaled addressing mode.
 
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
 ; Should not generate negated register offset
 
 define void @sintzero(i32* %a) nounwind {
@@ -23,6 +24,5 @@
 }
 
 ; CHECK: lsl{{.*}}#2]
-; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
-; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
+; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
 
Index: llvm/trunk/lib/Target/ARM/ARM.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td
+++ llvm/trunk/lib/Target/ARM/ARM.td
@@ -823,7 +823,8 @@
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
-def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52]>;
+def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52,
+                                                         FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description


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