[PATCH] D25485: [DAG] optimize negation of bool
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 17 14:37:04 PDT 2016
sdardis accepted this revision.
sdardis added a reviewer: sdardis.
sdardis added a comment.
This revision is now accepted and ready to land.
LGTM, unless ARM/PPC backend maintainers want to jump in. Two comments inlined.
> do you see any common folds that are missing based on the MIPS diffs?
I'm happy with codesize reduction in the microMIPS case, the missing fold/optimization case is subtraction by zero but that shouldn't hold this patch up. I'll deal with/work on the instruction count reduction change later.
Comment at: test/CodeGen/Mips/llvm-ir/add.ll:48-49
+ ; MMR6: andi16 $[[T0]], $[[T0]], 1
+ ; MMR6: li16 $[[T1:[0-9]+]], 0
+ ; MMR6: subu16 $[[T0]], $[[T1]], $[[T0]]
Add a comment above here along the lines of:
; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. This sequence is even better as it's a single instruction. See D25485 for the rest of the cases where this sequence occurs.
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:23-26
+; rUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
+; rUN: FileCheck %s -check-prefixes=ALL,64R6
+; rUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
+; rUN: FileCheck %s -check-prefixes=MM32,MM32R3
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