[PATCH] D25656: AMDGPU: Allow additional implicit operands on MOVRELS instructions
Nicolai Hähnle via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 16 06:14:38 PDT 2016
nhaehnle created this revision.
nhaehnle added reviewers: arsenm, tstellarAMD.
nhaehnle added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, wdng, kzhuravl.
The post-RA scheduler occasionally uses additional implicit operands when
the vector implicit operand as a whole is killed, but some subregisters
are still live because they are directly referenced later. Unfortunately,
this seems incredibly subtle to reproduce.
Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test
and others.
https://reviews.llvm.org/D25656
Files:
lib/Target/AMDGPU/SIInstrInfo.cpp
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2070,7 +2070,10 @@
Desc.getNumImplicitUses();
const unsigned NumImplicitOps = IsDst ? 2 : 1;
- if (MI.getNumOperands() != StaticNumOps + NumImplicitOps) {
+ // Allow additional implicit operands. This allows a fixup done by the post
+ // RA scheduler where the main implicit operand is killed and implicit-defs
+ // are added for sub-registers that remain live after this instruction.
+ if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
ErrInfo = "missing implicit register operands";
return false;
}
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