[llvm] r284306 - [X86] Regenerate known bits test

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Oct 15 13:56:38 2016
New Revision: 284306

URL: http://llvm.org/viewvc/llvm-project?rev=284306&view=rev
Log:
[X86] Regenerate known bits test

Modified:
    llvm/trunk/test/CodeGen/X86/computeKnownBits_urem.ll

Modified: llvm/trunk/test/CodeGen/X86/computeKnownBits_urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/computeKnownBits_urem.ll?rev=284306&r1=284305&r2=284306&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/computeKnownBits_urem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/computeKnownBits_urem.ll Sat Oct 15 13:56:38 2016
@@ -1,5 +1,21 @@
-; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
-define i32 @main() #0 {
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-linux | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64
+
+define i32 @main() nounwind {
+; X86-LABEL: main:
+; X86:       # BB#0: # %entry
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    movl $1, (%esp)
+; X86-NEXT:    movl $1, %eax
+; X86-NEXT:    popl %ecx
+; X86-NEXT:    retl
+;
+; X64-LABEL: main:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movl $1, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movl $1, %eax
+; X64-NEXT:    retq
 entry:
   %a = alloca i32, align 4
   store i32 1, i32* %a, align 4
@@ -10,5 +26,3 @@ entry:
   %add = add i32 %rem, 1
   ret i32 %add
 }
-; CHECK: $1, %eax
-; CHECK-NEXT: retq