[llvm] r284245 - [InstCombine] add tests for missing vector folds

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Oct 14 10:55:34 2016
New Revision: 284245

URL: http://llvm.org/viewvc/llvm-project?rev=284245&view=rev
Log:
[InstCombine] add tests for missing vector folds

Modified:
    llvm/trunk/test/Transforms/InstCombine/sub-xor.ll
    llvm/trunk/test/Transforms/InstCombine/sub.ll

Modified: llvm/trunk/test/Transforms/InstCombine/sub-xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sub-xor.ll?rev=284245&r1=284244&r2=284245&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sub-xor.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/sub-xor.ll Fri Oct 14 10:55:34 2016
@@ -12,6 +12,17 @@ define i32 @test1(i32 %x) {
   ret i32 %sub
 }
 
+define <2 x i32> @test1vec(<2 x i32> %x) {
+; CHECK-LABEL: @test1vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> %x, <i32 31, i32 31>
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> <i32 63, i32 63>, [[AND]]
+; CHECK-NEXT:    ret <2 x i32> [[SUB]]
+;
+  %and = and <2 x i32> %x, <i32 31, i32 31>
+  %sub = sub <2 x i32> <i32 63, i32 63>, %and
+  ret <2 x i32> %sub
+}
+
 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
 
 define i32 @test2(i32 %x) nounwind {

Modified: llvm/trunk/test/Transforms/InstCombine/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sub.ll?rev=284245&r1=284244&r2=284245&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sub.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/sub.ll Fri Oct 14 10:55:34 2016
@@ -152,6 +152,28 @@ define i32 @test13(i32 %A) {
   ret i32 %C
 }
 
+define <2 x i32> @test12vec(<2 x i32> %A) {
+; CHECK-LABEL: @test12vec(
+; CHECK-NEXT:    [[B:%.*]] = ashr <2 x i32> %A, <i32 31, i32 31>
+; CHECK-NEXT:    [[C:%.*]] = sub nsw <2 x i32> zeroinitializer, [[B]]
+; CHECK-NEXT:    ret <2 x i32> [[C]]
+;
+  %B = ashr <2 x i32> %A, <i32 31, i32 31>
+  %C = sub <2 x i32> zeroinitializer, %B
+  ret <2 x i32> %C
+}
+
+define <2 x i32> @test13vec(<2 x i32> %A) {
+; CHECK-LABEL: @test13vec(
+; CHECK-NEXT:    [[B:%.*]] = lshr <2 x i32> %A, <i32 31, i32 31>
+; CHECK-NEXT:    [[C:%.*]] = sub nsw <2 x i32> zeroinitializer, [[B]]
+; CHECK-NEXT:    ret <2 x i32> [[C]]
+;
+  %B = lshr <2 x i32> %A, <i32 31, i32 31>
+  %C = sub <2 x i32> zeroinitializer, %B
+  ret <2 x i32> %C
+}
+
 define i32 @test15(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test15(
 ; CHECK-NEXT:    [[C:%.*]] = sub i32 0, %A