[PATCH] D25577: AMDGPU/SI: Handle hazard with > 8 byte VMEM stores

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:384-391
+      // For MUBUF/MTBUF instructions this hazard only exists if the
+      // instruction is not using a register in the soffset field.
+      const MachineOperand *SOffset =
+          TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
+      // If we have no soffset operand, then assume this field has been
+      // hardcoded to zero.
+      if (VDataRC->getSize() > 8 && (!SOffset || !SOffset->isReg()))
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2 space indent


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:397
+  // of their dmask set.
+  // All our MIMG definitions use a 256-bit T#, so we can skip checking for them.
+
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this should maybe assert


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:412-414
+  // This checks for the hazard where VMEM instructions that store more than
+  // 8 bytes can have there store data over written by the next instruction.
+  if (ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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Maybe this should move into an ST.hasFooHazard() check (and be just == SOUTHERN_ISLANDS)


https://reviews.llvm.org/D25577