[PATCH] D25551: AMDGPU: Implement SGPR spilling with scalar stores

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl, qcolombet.
Herald added a reviewer: tstellarAMD.

This avoids the nasty problems caused by using
memory instructions that read the exec mask while
spilling / restoring registers used for control flow
masking, but only for VI when these were added.

      

This always uses the scalar stores when enabled currently,
but it may be better to still try to spill to a VGPR
and use this on the fallback memory path.

      

The cache also needs to be flushed before wave termination
if a scalar store is used.


https://reviews.llvm.org/D25551

Files:
  lib/Target/AMDGPU/SIInsertWaits.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
  test/CodeGen/AMDGPU/basic-branch.ll
  test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  test/CodeGen/AMDGPU/spill-m0.ll
  test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir

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