[llvm] r283971 - [AArch64][InstructionSelector] Fix typos in the related mir file. NFC.

Quentin Colombet via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 11 20:57:46 PDT 2016


Author: qcolombet
Date: Tue Oct 11 22:57:46 2016
New Revision: 283971

URL: http://llvm.org/viewvc/llvm-project?rev=283971&view=rev
Log:
[AArch64][InstructionSelector] Fix typos in the related mir file. NFC.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=283971&r1=283970&r2=283971&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Tue Oct 11 22:57:46 2016
@@ -1290,6 +1290,7 @@ registers:
 # CHECK: %2 = ADDXrr %0, %1
 body:             |
   bb.0:
+      liveins: %x0
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT 42
     %2(p0) = G_GEP %0, %1(s64)
@@ -1350,7 +1351,7 @@ registers:
 # CHECK:    %3 = COPY %2
 body:             |
   bb.0:
-    liveins: %x0
+    liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
@@ -1384,7 +1385,7 @@ registers:
 # CHECK:    %3 = UBFMWri %2, 0, 7
 body:             |
   bb.0:
-    liveins: %x0
+    liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
@@ -1418,7 +1419,7 @@ registers:
 # CHECK:    %3 = SBFMWri %2, 0, 7
 body:             |
   bb.0:
-    liveins: %x0
+    liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0




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