[llvm] r283930 - [x86] add tests for negate bool

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Tue Oct 11 15:15:20 2016
New Revision: 283930

URL: http://llvm.org/viewvc/llvm-project?rev=283930&view=rev
Log:
[x86] add tests for negate bool

Added:
    llvm/trunk/test/CodeGen/X86/negate-i1.ll

Added: llvm/trunk/test/CodeGen/X86/negate-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/negate-i1.ll?rev=283930&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/negate-i1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/negate-i1.ll Tue Oct 11 15:15:20 2016
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @select_i8_neg1_or_0(i1 %a) {
+; CHECK-LABEL: select_i8_neg1_or_0:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    shlb $7, %dil
+; CHECK-NEXT:    sarb $7, %dil
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i8
+  ret i8 %b
+}
+
+define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
+; CHECK-LABEL: select_i8_neg1_or_0_zeroext:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    shlb $7, %dil
+; CHECK-NEXT:    sarb $7, %dil
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i8
+  ret i8 %b
+}
+
+define i16 @select_i16_neg1_or_0(i1 %a) {
+; CHECK-LABEL: select_i16_neg1_or_0:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    shll $15, %edi
+; CHECK-NEXT:    sarw $15, %di
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i16
+  ret i16 %b
+}
+
+define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
+; CHECK-LABEL: select_i16_neg1_or_0_zeroext:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    shll $15, %eax
+; CHECK-NEXT:    sarw $15, %ax
+; CHECK-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i16
+  ret i16 %b
+}
+
+define i32 @select_i32_neg1_or_0(i1 %a) {
+; CHECK-LABEL: select_i32_neg1_or_0:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    shll $31, %edi
+; CHECK-NEXT:    sarl $31, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i32
+  ret i32 %b
+}
+
+define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
+; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    shll $31, %eax
+; CHECK-NEXT:    sarl $31, %eax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i32
+  ret i32 %b
+}
+
+define i64 @select_i64_neg1_or_0(i1 %a) {
+; CHECK-LABEL: select_i64_neg1_or_0:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT:    shlq $63, %rdi
+; CHECK-NEXT:    sarq $63, %rdi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i64
+  ret i64 %b
+}
+
+define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
+; CHECK-LABEL: select_i64_neg1_or_0_zeroext:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    shlq $63, %rax
+; CHECK-NEXT:    sarq $63, %rax
+; CHECK-NEXT:    retq
+;
+  %b = sext i1 %a to i64
+  ret i64 %b
+}
+