[PATCH] D23566: [RISCV 8/10] Add support for all RV32I instructions

[Alex Bradbury via llvm-commits]

asb updated this revision to Diff 74026.
asb marked 5 inline comments as done.
asb added a comment.

Make use of isShiftedInt from MathExtras.h. Rename `{simm21,simm13}_mask1` to `{simm21,simm13}_lsb0`. Tests are updated to check instruction printing.


https://reviews.llvm.org/D23566

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/rv32i-invalid.s
  test/MC/RISCV/rv32i-valid.s

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