[PATCH] D25301: CodeGen: Sign extend immediates passed to FastISel entry points instead of zero extending them.

[Peter Collingbourne via llvm-commits]

pcc created this revision.
pcc added a reviewer: chandlerc.
pcc added a subscriber: llvm-commits.
Herald added a subscriber: nemanjai.

The purpose of this change is to ensure that ImmLeaf predicates are evaluated
consistently between SelectionDAG and FastISel. This is necessary for an
upcoming change that will allow ImmLeaf predicates to take a zero extended
immediate.

The test case change is benign; the high bits of the value being loaded into
the register are masked off by a later instruction.


https://reviews.llvm.org/D25301

Files:
  llvm/include/llvm/CodeGen/FastISel.h
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
  llvm/utils/TableGen/FastISelEmitter.cpp

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