[llvm] r283327 - Revert "[mips] Add rsqrt, recip for MIPS"
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 5 08:28:34 PDT 2016
Author: sdardis
Date: Wed Oct 5 10:28:33 2016
New Revision: 283327
URL: http://llvm.org/viewvc/llvm-project?rev=283327&view=rev
Log:
Revert "[mips] Add rsqrt, recip for MIPS"
This reverts commit r282485 which contain two patches instead of
one.
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSchedule.td
llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
llvm/trunk/test/MC/Mips/macro-li-bad.s
llvm/trunk/test/MC/Mips/macro-li.s
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips4/valid-xfail.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Oct 5 10:28:33 2016
@@ -995,7 +995,7 @@ public:
void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
uint64_t Imm = getConstantImm() - Offset;
- Imm &= (1ULL << Bits) - 1;
+ Imm &= (1 << Bits) - 1;
Imm += Offset;
Imm += AdjustOffset;
Inst.addOperand(MCOperand::createImm(Imm));
@@ -1093,8 +1093,7 @@ public:
bool isRegIdx() const { return Kind == k_RegisterIndex; }
bool isImm() const override { return Kind == k_Immediate; }
bool isConstantImm() const {
- int64_t Res;
- return isImm() && getImm()->evaluateAsAbsolute(Res);
+ return isImm() && isa<MCConstantExpr>(getImm());
}
bool isConstantImmz() const {
return isConstantImm() && getConstantImm() == 0;
@@ -1265,9 +1264,7 @@ public:
int64_t getConstantImm() const {
const MCExpr *Val = getImm();
- int64_t Value = 0;
- (void)Val->evaluateAsAbsolute(Value);
- return Value;
+ return static_cast<const MCConstantExpr *>(Val)->getValue();
}
MipsOperand *getMemBase() const {
@@ -4054,9 +4051,6 @@ bool MipsAsmParser::MatchAndEmitInstruct
case Match_SImm32_Relaxed:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 32-bit signed immediate");
- case Match_UImm32_Coerced:
- return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
- "expected 32-bit immediate");
case Match_MemSImm9:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected memory with 9-bit signed offset");
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Oct 5 10:28:33 2016
@@ -186,6 +186,8 @@ class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
+class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
+class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
@@ -196,6 +198,8 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MM
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
+class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
+class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
@@ -1114,6 +1118,14 @@ class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DE
II_SQRT_S, fsqrt>;
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
II_SQRT_D, fsqrt>;
+class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
+ FGR32Opnd, II_TRUNC>;
+class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
+ AFGR64Opnd, II_TRUNC>;
+class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
+ FGR32Opnd, II_ROUND>;
+class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
+ II_ROUND>;
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
FGR32Opnd, II_ROUND>;
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
@@ -1652,6 +1664,10 @@ def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR
ISA_MICROMIPS32R6;
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
ISA_MICROMIPS32R6;
+def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1692,6 +1708,9 @@ def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_
def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
+def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Wed Oct 5 10:28:33 2016
@@ -141,16 +141,6 @@ let AdditionalPredicates = [InMicroMips]
MFC1_FM_MM<0x40>;
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
MFC1_FM_MM<0x60>;
- def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
- II_RECIP_S>,
- ROUND_W_FM_MM<0b0, 0b01001000>;
- def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
- II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
- def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
- II_RECIP_S>,
- ROUND_W_FM_MM<0b0, 0b00001000>;
- def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
- II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
}
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Oct 5 10:28:33 2016
@@ -284,16 +284,6 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CE
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
-let AdditionalPredicates = [NotInMicroMips] in {
- def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
- ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
- def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
- ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
- def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
- ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
- def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
- ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
-}
let DecoderNamespace = "Mips64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Oct 5 10:28:33 2016
@@ -300,9 +300,6 @@ class INSN_MIPS3_32_NOT_32R6_64R6 {
// The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
-// The portions of MIPS-IV that were also added to MIPS32.
-class INSN_MIPS4_32 { list <Predicate> InsnPredicates = [HasMips4_32]; }
-
// The portions of MIPS-IV that were also added to MIPS32 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS4_32_NOT_32R6_64R6 {
@@ -315,11 +312,6 @@ class INSN_MIPS4_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
}
-// The portions of MIPS-IV that were also added to MIPS32r2.
-class INSN_MIPS4_32R2 {
- list<Predicate> InsnPredicates = [HasMips4_32r2];
-}
-
// The portions of MIPS-V that were also added to MIPS32r2 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS5_32R2_NOT_32R6_64R6 {
@@ -467,16 +459,6 @@ class UImmAsmOperandClass<int Bits, list
let DiagnosticType = "UImm" # Bits;
}
-// Generic case - only to support certain assembly pseudo instructions.
-class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
- : AsmOperandClass {
- let Name = "ImmAny";
- let RenderMethod = "addConstantUImmOperands<32>";
- let PredicateMethod = "isSImm<" # Bits # ">";
- let SuperClasses = Supers;
- let DiagnosticType = "ImmAny";
-}
-
// AsmOperandClasses require a strict ordering which is difficult to manage
// as a hierarchy. Instead, we use a linear ordering and impose an order that
// is in some places arbitrary.
@@ -500,13 +482,8 @@ class UImmAnyAsmOperandClass<int Bits, l
// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
// This is entirely arbitrary. We need an ordering and what we pick is
// unimportant since only one is possible for a given mnemonic.
-
-def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
- let Name = "UImm32_Coerced";
- let DiagnosticType = "UImm32_Coerced";
-}
def SImm32RelaxedAsmOperandClass
- : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
+ : SImmAsmOperandClass<32, []> {
let Name = "SImm32_Relaxed";
let PredicateMethod = "isAnyImm<32>";
let DiagnosticType = "SImm32_Relaxed";
@@ -530,8 +507,6 @@ def UImm16RelaxedAsmOperandClass
let PredicateMethod = "isAnyImm<16>";
let DiagnosticType = "UImm16_Relaxed";
}
-// FIXME: One of these should probably have UImm16AsmOperandClass as the
-// superclass instead of UImm16RelaxedasmOPerandClass.
def UImm16AsmOperandClass
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
def SImm16RelaxedAsmOperandClass
@@ -889,10 +864,6 @@ def simm16_64 : Operand<i64> {
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
}
-// like simm32 but coerces simm32 to uimm32.
-def uimm32_coerced : Operand<i32> {
- let ParserMatchClass = !cast<AsmOperandClass>("UImm32CoercedAsmOperandClass");
-}
// Like simm32 but coerces uimm32 to simm32.
def simm32_relaxed : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
@@ -2408,12 +2379,11 @@ def : MipsInstAlias<"sync",
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
-// We use uimm32_coerced to accept a 33 bit signed number that is rendered into
-// a 32 bit number.
+// We use i32imm on li/la to defer range checking to the assembler.
class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
!strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>;
+def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>;
class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
RegisterOperand RO> :
Modified: llvm/trunk/lib/Target/Mips/MipsSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSchedule.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSchedule.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsSchedule.td Wed Oct 5 10:28:33 2016
@@ -270,15 +270,11 @@ def II_ORI : InstrItinClass
def II_POP : InstrItinClass;
def II_RDHWR : InstrItinClass;
def II_RESTORE : InstrItinClass;
-def II_RECIP_S : InstrItinClass;
-def II_RECIP_D : InstrItinClass;
def II_RINT_S : InstrItinClass;
def II_RINT_D : InstrItinClass;
def II_ROTR : InstrItinClass;
def II_ROTRV : InstrItinClass;
def II_ROUND : InstrItinClass;
-def II_RSQRT_S : InstrItinClass;
-def II_RSQRT_D : InstrItinClass;
def II_SAVE : InstrItinClass;
def II_SC : InstrItinClass;
def II_SCD : InstrItinClass;
@@ -611,10 +607,6 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
- InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>,
- InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>,
- InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>,
- InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>,
InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
Modified: llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td Wed Oct 5 10:28:33 2016
@@ -440,10 +440,6 @@ def : ItinRW<[GenericWriteFPUDivD], [II_
def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>;
def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>;
-// rsqrt.[ds], recip.[ds]
-def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>;
-def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>;
-
// MIPSR6
// ======
//
Modified: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td Wed Oct 5 10:28:33 2016
@@ -448,9 +448,6 @@ def : ItinRW<[P5600WriteFPUSqrtD], [II_S
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
-def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
-def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
-
// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
// fsub.[wd]
def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Wed Oct 5 10:28:33 2016
@@ -195,7 +195,3 @@
0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
-0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
-0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
-0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
-0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Wed Oct 5 10:28:33 2016
@@ -199,7 +199,3 @@
0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
-0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
-0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
-0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
-0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt Wed Oct 5 10:28:33 2016
@@ -135,12 +135,8 @@
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt Wed Oct 5 10:28:33 2016
@@ -286,10 +286,6 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt Wed Oct 5 10:28:33 2016
@@ -70,9 +70,13 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt Wed Oct 5 10:28:33 2016
@@ -129,14 +129,10 @@
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt Wed Oct 5 10:28:33 2016
@@ -283,10 +283,6 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt Wed Oct 5 10:28:33 2016
@@ -70,9 +70,13 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt Wed Oct 5 10:28:33 2016
@@ -131,12 +131,8 @@
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt Wed Oct 5 10:28:33 2016
@@ -284,10 +284,6 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt Wed Oct 5 10:28:33 2016
@@ -70,9 +70,13 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt Wed Oct 5 10:28:33 2016
@@ -125,12 +125,8 @@
0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt Wed Oct 5 10:28:33 2016
@@ -134,10 +134,6 @@
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt Wed Oct 5 10:28:33 2016
@@ -155,15 +155,11 @@
0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7
0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
-0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5)
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
+0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5)
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4
0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14)
0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt Wed Oct 5 10:28:33 2016
@@ -257,7 +257,3 @@
0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13)
0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18)
0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt Wed Oct 5 10:28:33 2016
@@ -36,3 +36,7 @@
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt Wed Oct 5 10:28:33 2016
@@ -206,10 +206,6 @@
0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
0xcf 0x01 0x00 0x00 # CHECK: sync 7
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt Wed Oct 5 10:28:33 2016
@@ -73,4 +73,8 @@
0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26
0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt Wed Oct 5 10:28:33 2016
@@ -331,10 +331,6 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt Wed Oct 5 10:28:33 2016
@@ -193,16 +193,12 @@
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt Wed Oct 5 10:28:33 2016
@@ -363,10 +363,6 @@
0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt Wed Oct 5 10:28:33 2016
@@ -67,6 +67,10 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt Wed Oct 5 10:28:33 2016
@@ -190,16 +190,12 @@
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt Wed Oct 5 10:28:33 2016
@@ -351,12 +351,8 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
-0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
-0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
+0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
+0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27
0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt Wed Oct 5 10:28:33 2016
@@ -67,6 +67,10 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt Wed Oct 5 10:28:33 2016
@@ -190,16 +190,12 @@
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt Wed Oct 5 10:28:33 2016
@@ -351,10 +351,6 @@
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt Wed Oct 5 10:28:33 2016
@@ -67,6 +67,10 @@
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt Wed Oct 5 10:28:33 2016
@@ -156,12 +156,8 @@
0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
-0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
-0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
-0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
-0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp)
0x0e 0x00 0x00 0x00 # CHECK: sdbbp
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt Wed Oct 5 10:28:33 2016
@@ -153,10 +153,6 @@
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12
Modified: llvm/trunk/test/MC/Mips/macro-li-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-li-bad.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-li-bad.s (original)
+++ llvm/trunk/test/MC/Mips/macro-li-bad.s Wed Oct 5 10:28:33 2016
@@ -7,5 +7,5 @@
.text
li $5, 0x100000000
- # 32-BIT: :[[@LINE-1]]:10: error: expected 32-bit immediate
- # 64-BIT: :[[@LINE-2]]:10: error: expected 32-bit immediate
+ # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+ # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
Modified: llvm/trunk/test/MC/Mips/macro-li.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-li.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-li.s (original)
+++ llvm/trunk/test/MC/Mips/macro-li.s Wed Oct 5 10:28:33 2016
@@ -65,11 +65,3 @@ li $5, 0xc0008000 # CHECK: lui $5, 49152
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
-li $4, ~0xffffffff # CHECK; addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00]
-li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]
- # CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe]
-li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]
- # CHECK: ori $4, $4, 65535 # encoding: [0x34,0x84,0xff,0xff]
-li $4, ~0x7fffffff # CHECK: lui $4, 32768 # encoding: [0x3c,0x04,0x80,0x00]
-li $4, ~0x00000001 # CHECK: addiu $4, $zero, -2 # encoding: [0x24,0x04,0xff,0xfe]
-li $4, ~0x00000000 # CHECK: addiu $4, $zero, -1 # encoding: [0x24,0x04,0xff,0xff]
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Wed Oct 5 10:28:33 2016
@@ -203,7 +203,3 @@ cfc1 $1, $2 # CHECK: cfc
cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c]
ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b]
ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c]
-recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
-recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
-rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b]
-rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -102,9 +102,13 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Wed Oct 5 10:28:33 2016
@@ -167,15 +167,11 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -102,9 +102,13 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Wed Oct 5 10:28:33 2016
@@ -167,15 +167,11 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -102,9 +102,13 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Wed Oct 5 10:28:33 2016
@@ -168,15 +168,11 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Wed Oct 5 10:28:33 2016
@@ -139,8 +139,6 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
@@ -187,8 +185,6 @@ a:
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips4/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -35,3 +35,7 @@
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
+ recip.d $f19,$f6
+ recip.s $f3,$f30
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Wed Oct 5 10:28:33 2016
@@ -196,14 +196,10 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -72,4 +72,8 @@
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
+ recip.d $f19,$f6
+ recip.s $f3,$f30
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Wed Oct 5 10:28:33 2016
@@ -197,14 +197,10 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips64/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -79,4 +79,8 @@
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
+ recip.d $f19,$f6
+ recip.s $f3,$f30
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Wed Oct 5 10:28:33 2016
@@ -213,14 +213,10 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -101,7 +101,11 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Wed Oct 5 10:28:33 2016
@@ -234,8 +234,6 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
@@ -243,8 +241,6 @@ a:
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -104,7 +104,11 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Wed Oct 5 10:28:33 2016
@@ -234,8 +234,6 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
@@ -243,8 +241,6 @@ a:
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s Wed Oct 5 10:28:33 2016
@@ -104,7 +104,11 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
+ recip.d $f19,$f6
+ recip.s $f3,$f30
rorv $13,$a3,$s5
+ rsqrt.d $f3,$f28
+ rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Wed Oct 5 10:28:33 2016
@@ -235,8 +235,6 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
@@ -244,8 +242,6 @@ a:
round.l.s $f25,$f5
round.w.d $f6,$f4
round.w.s $f27,$f28
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14)
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=283327&r1=283326&r2=283327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Wed Oct 5 10:28:33 2016
@@ -194,12 +194,8 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
- recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a]
- rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
- rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
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