[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

Some quick remarks - I'll do more of review later after others have had a chance to look at it.



> X86ISelLowering.cpp:29016
> +    return SDValue();
> +
> +  // Check the OR user is a zero extend and that it is extending to 32-bit or

Should we return early if !Subtarget.isCtlzFast()?

> X86ISelLowering.cpp:29022
> +      !N->use_begin()->getSimpleValueType(0).bitsGE(MVT::i32))
> +    return SDValue();
> +

Are we letting vector types through here?

> X86ISelLowering.cpp:31797
> +  if(Opc == ISD::SRL && VT != MVT::i32 && VT != MVT::i8)
> +    return false;
>    if (VT != MVT::i16)

Comment this. Should this be part of a separate patch with its own tests? Its fine if its only exposed by this patch to leave it here, but it should have a comment either way.

> lzcnt-zext-cmp.ll:7
> +
> +; Test two 32-bit inputs, output is 32-bit.
> +define i32 @bar1(i32 %a, i32 %b) {

Test single input version to make sure it isn't being used.

https://reviews.llvm.org/D23446