[lld] r282671 - [AArch64] Fix test case ELF/aarch64-tls-le.s

[Lei Liu via llvm-commits]

Author: lliu0
Date: Wed Sep 28 21:01:27 2016
New Revision: 282671

URL: http://llvm.org/viewvc/llvm-project?rev=282671&view=rev
Log:
[AArch64] Fix test case ELF/aarch64-tls-le.s

The add instruction should be generated with shift bit (lsl #12).
Update the test case.


Modified:
    lld/trunk/test/ELF/aarch64-tls-le.s

Modified: lld/trunk/test/ELF/aarch64-tls-le.s
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/aarch64-tls-le.s?rev=282671&r1=282670&r2=282671&view=diff
==============================================================================
--- lld/trunk/test/ELF/aarch64-tls-le.s (original)
+++ lld/trunk/test/ELF/aarch64-tls-le.s Wed Sep 28 21:01:27 2016
@@ -18,7 +18,7 @@ _start:
 #CHECK: Disassembly of section .text:
 #CHECK: _start:
 #CHECK:  11000: 40 d0 3b d5     mrs     x0, TPIDR_EL0
-#CHECK:  11004: 00 00 00 91     add     x0, x0, #0
+#CHECK:  11004: 00 00 40 91     add     x0, x0, #0, lsl #12
 #CHECK:  11008: 00 40 00 91     add     x0, x0, #16
 
 .type   v1, at object